Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness

Yuan WANG  Guangyi LU  Yize WANG  Xing ZHANG  

IEICE TRANSACTIONS on Electronics   Vol.E100-C   No.3   pp.344-347
Publication Date: 2017/03/01
Online ISSN: 1745-1353
Type of Manuscript: BRIEF PAPER
Category: Semiconductor Materials and Devices
electrostatic discharge (ESD),  robustness,  false-triggering immunity,  transmission-line-pulsing (TLP) test,  

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This work reports a novel power-rail electrostatic discharge (ESD) clamp circuit with parasitic bipolar-junction-transistor (BJT) and channel parallel shunt paths. The parallel shunt paths are formed by delivering a tiny ratio of drain voltage to the gate terminal of the clamp device in ESD events. Under such a mechanism, the proposed circuit achieves enhanced robustness over those of both gate-grounded NMOS (ggNMOS) and the referenced gate-coupled NMOS (gcNMOS). Besides, the proposed circuit also achieves improved fast power-up immunity over that of the referenced gcNMOS. All investigated designs are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and human-body-model (HBM) test results have both confirmed the performance enhancements of the proposed circuit. Finally, the validity of the achieved performance enhancements on other trigger circuits is essentially revealed in this work.