A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI

Aravind THARAYIL NARAYANAN  Wei DENG  Dongsheng YANG  Rui WU  Kenichi OKADA  Akira MATSUZAWA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E100-C   No.3   pp.259-267
Publication Date: 2017/03/01
Online ISSN: 1745-1353
Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
fully-synthesizable,  all-digital,  clock data recovery,  injection locking,  phase-filtering,  

Full Text: PDF(3.8MB)
>>Buy this Article


Summary: 
An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.