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Efficient Multiplexer Networks for FieldData Extractors and Their Evaluations
Koki ITO Kazushi KAWAMURA Yutaka TAMIYA Masao YANAGISAWA Nozomu TOGAWA
Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Vol.E100A
No.4
pp.10151028 Publication Date: 2017/04/01
Online ISSN: 17451337 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: fielddata extractor, multiplexer network, partitioning, rotator,
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Summary:
As seen in stream data processing, it is necessary to extract a particular data field from bulk data, where we can use a fielddata extractor. Particularly, an (M,N)fielddata extractor reads out any consecutive N bytes from an Mbyte register by connecting its input/output using multiplexers (MUXs). However, the number of required MUXs increases too much as the input/output byte widths increase. It is known that partitioning a MUX network leads to reducing the number of MUXs. In this paper, we firstly pick up a multilayered MUX network, which is generated by repeatedly partitioning a MUX network into a collection of singlelayered MUX networks. We show that the multilayered MUX network is equivalent to the barrel shifter from which redundant MUXs and wires are removed, and we prove that the number of required MUXs becomes the smallest among MUXnetworkpartitioning based fielddata extractors. Next, we propose a rotatorbased MUX network for a fielddata extractor, which is based on reading out a particular data in an input register to a rotator. The byte width of the rotator is the same as its output register and hence we no longer require any extra wires nor MUXs. By rotating the input data appropriately, we can finally have a rightordered data into an output register. Experimental results show that a multilayered MUX network reduces the number of required gates to construct a fielddata extractor by up to 97.0% compared with the one using a naive approach and its delay becomes 1.8ns2.3ns. A rotatorbased MUX network with a control circuit also reduces the number of required gates to construct a fielddata extractor by up to 97.3% compared with the one using a naive approach and its delay becomes 2.1ns2.9ns.

