lq Sparsity Penalized STAP Algorithm with Sidelobe Canceler Architecture for Airborne Radar

Xiaoxia DAI  Wei XIA  Wenlong HE  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E100-A   No.2   pp.729-732
Publication Date: 2017/02/01
Online ISSN: 1745-1337
DOI: 10.1587/transfun.E100.A.729
Type of Manuscript: LETTER
Category: Information Theory
STAP,  sparsity aware,  lq penalty,  penalized least squares,  cyclic descent,  

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Much attention has recently been paid to sparsity-aware space-time adaptive processing (STAP) algorithms. The idea of sparsity-aware technology is commonly based on the convex l1-norm penalty. However, some works investigate the lq (0 < q < 1) penalty which induces more sparsity owing to its lack of convexity. We herein consider the design of an lq penalized STAP processor with a generalized sidelobe canceler (GSC) architecture. The lq cyclic descent (CD) algorithm is utilized with the least squares (LS) design criterion. It is validated through simulations that the lq penalized STAP processor outperforms the existing l1-based counterparts in both convergence speed and steady-state performance.