An Error Correction Method for Neighborhood-Level Errors in NAND Flash Memories

Shohei KOTAKI  Masato KITAKAMI  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E100-A   No.2   pp.653-662
Publication Date: 2017/02/01
Online ISSN: 1745-1337
Type of Manuscript: PAPER
Category: Coding Theory
Keyword: 
error correcting codes,  NAND Flash memories,  multilevel cell,  limited-magnitude errors,  multipage programming,  

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Summary: 
Rapid process scaling and the introduction of the multilevel cell (MLC) concept have lowered costs of NAND Flash memories, but also degraded reliability. For this reason, the memories are depending on strong error correcting codes (ECCs), and this has enabled the memories to be used in wide range of storage applications, including solid-state drives (SSDs). Meanwhile, too strong error correcting capability requires excessive decoding complexity and check bits. In NAND Flash memories, cell errors to neighborhood voltage levels are more probable than those to distant levels. Several ECCs reflecting this characteristics, including limited-magnitude ECCs which correct only errors with a certain limited magnitude and low-density parity check (LDPC) codes, have been proposed. However, as most of these ECCs need the multiple bits in a cell for encoding, they cannot be used with multipage programing, a high speed programming method currently employed in the memories. Also, binary ECCs with Gray codes are no longer optimal when multilevel voltage shifts (MVSs) occur. In this paper, an error correction method reflecting the error characteristic is presented. This method detects errors by a binary ECC as a conventional manner, but a nonbinary value or whole the bits in a cell, are subjected to error correction, so as to be corrected into the most probable neighborhood value. The amount of bit error rate (BER) improvement is depending on the probability of the each error magnitude. In case of 2bit/cell, if only errors of magnitude 1 and 2 can occur and the latter occupies 5% of cell errors, acceptable BER is improved by 4%. This is corresponding to extending 2.4% of endurance. This method needs about 15% longer average latency, 19% longer maximum latency, and 15% lower throughput. However, with using the conventional method until the memories' lifetime number of program/erase cycling, and the proposed method after that, BER improvement can be utilized for extending endurance without latency and throughput degradation until the switch of the methods.