For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
A Hardware Efficient Multiple-Stream Pipeline FFT Processor for MIMO-OFDM Systems
Kai-Feng XIA Bin WU Tao XIONG Tian-Chun YE Cheng-Ying CHEN
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2017/02/01
Online ISSN: 1745-1337
Type of Manuscript: PAPER
Category: Digital Signal Processing
multiple-input and multiple-output (MIMO), pipeline FFT processor, multipath delay feedback (MDF), multipath delay commutator (MDC), bit-reversal circuits, long term evolution (LTE),
Full Text: PDF(2.9MB)
>>Buy this Article
In this paper, a hardware efficient design methodology for a configurable-point multiple-stream pipeline FFT processor is presented. We first compared the memory and arithmetic components of different pipeline FFT architectures, and obtained the conclusion that MDF architecture is more hardware efficient than MDC for the overall processor. Then, in order to reduce the computational complexity, a binary-tree representation was adopted to analyze the decomposition algorithm. Consequently, the coefficient multiplications are minimized among all the decomposition probabilities. In addition, an efficient output reorder circuit was designed for the multiple-stream architecture. An 128∼2048 point 4-stream FFT processor in LTE system was designed in SMIC 55nm technology for evaluation. It owns 1.09mm2 core area with 82.6mW power consumption at 122.88MHz clock frequency.