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Keyword : within-die variation

Way-Scaling to Reduce Power of Cache with Delay Variation Maziar GOUDARZI Tadayuki MATSUMURA Tohru ISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3576-3584 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: leakage, power reduction, cache, within-die variation, delay variation, way scaling,
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Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis Masakazu AOKI Shin-ichi OHKAWA Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 647-654 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: modeling transistor variations, within-die variation, statistical analysis for transistor parameters, SRAM cell sensitivity analysis, process window for SRAM cell operation,
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A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations Kazuya KATSUKI Manabu KOTANI Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 699-707 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: within-die variation, reconfigurable device, FPGA, LUT (look-up table), yield,
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