Keyword : wafer scale integration


A System for Efficiently Self-Reconstructing 1(1/2)-Track Switch Torus Arrays
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/12/01
Vol. E84-D  No. 12 ; pp. 1801-1809
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
reconfiguration1(1/2)-track switch torus arrayfault tolerancewafer scale integrationself-reconfigurable system
 Summary | Full Text:PDF(787.5KB)

The Evolutionary Algorithm-Based Reasoning System
Moritoshi YASUNAGA Ikuo YOSHIHARA Jung Hwan KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/11/01
Vol. E84-D  No. 11 ; pp. 1508-1520
Type of Manuscript:  Special Section PAPER (Special Issue on Function Integrated Information Systems)
Category: 
Keyword: 
evolutionary algorithmreasoningFPGAwafer scale integrationfault tolerance
 Summary | Full Text:PDF(2.5MB)

An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/08/25
Vol. E83-D  No. 8 ; pp. 1701-1705
Type of Manuscript:  LETTER
Category: Fault Tolerance
Keyword: 
fault tolerant processor arrays1 1/2 track-switch modelself-reconfigurable systemrun-time fault tolerancewafer scale integration
 Summary | Full Text:PDF(662.1KB)

An Efficient Method for Reconfiguring the 1 1/2 Track-Switch Mesh Array
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/12/25
Vol. E82-D  No. 12 ; pp. 1545-1553
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
mesh-connected parallel computerwafer scale integrationyield enhancementfault tolerance1 1/2 track-switch model
 Summary | Full Text:PDF(962.4KB)

An Efficiently Reconfigurable Architecture for Mesh-Arrays with PE and Link Faults
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/09/25
Vol. E80-D  No. 9 ; pp. 879-885
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Fault Tolerance
Keyword: 
mesh-arraydefect tolerancelink faultPE faultwafer scale integration
 Summary | Full Text:PDF(515KB)

A Built-In Self-Reconstruction Approach for Partitioned Mesh-Arrays Using Neural Algorithm
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8 ; pp. 1160-1167
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Fault Diagnosis/Tolerance
Keyword: 
mesh-arrayfault toleranceself-reconfigurable systemwafer scale integrationneural algorithm
 Summary | Full Text:PDF(557.5KB)