IEICE SEARCH SYSTEM

Keyword : verification

A Verification-Aware Design Methodology for Thread Pipelining Parallelization Guo-An JIAN Cheng-An CHIEN Peng-Sheng CHEN Jiun-In GUO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/10/01 Vol. E95-D No. 10 pp. 2505-2513 Type of Manuscript: PAPER Category: Image Processing and Video Processing Keyword: verification, 3D depth map generation, pipeline, parallel computing, behavior model,
	Summary \| Full Text:PDF (1.7MB)

Decidability of the Security against Inference Attacks Using a Functional Dependency on XML Databases Kenji HASHIMOTO Hiroto KAWAI Yasunori ISHIHARA Toru FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/05/01 Vol. E95-D No. 5 pp. 1365-1374 Type of Manuscript: Special Section PAPER (Special Section on Formal Approach) Category: Database Security Keyword: XML database, inference attack, security, verification, functional dependency,
	Summary \| Full Text:PDF (608.8KB)

Workflows with Passbacks and Incremental Verification of Their Correctness Osamu TAKAKI Izumi TAKEUTI Noriaki IZUMI Koiti HASIDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/04/01 Vol. E95-D No. 4 pp. 989-1002 Type of Manuscript: Special Section PAPER (Special Section on Knowledge-Based Software Engineering) Category: Keyword: workflow, verification, correctness, passback, incremental verification,
	Summary \| Full Text:PDF (726.2KB)

Narrow Fingerprint Sensor Verification with Template Updating Technique SangWoo SIN Ru ZHOU Dongju LI Tsuyoshi ISSHIKI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/01/01 Vol. E95-A No. 1 pp. 346-353 Type of Manuscript: PAPER Category: Algorithms and Data Structures Keyword: fingerprint, biometric, verification, template updating, narrow fingerprint sensor,
	Summary \| Full Text:PDF (2MB)

A Verification and Analysis Tool Set for Embedded System Design Yuichi NAKAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2788-2793 Type of Manuscript: Special Section PAPER (Special Section on Mathematical Systems Science and its Applications) Category: INVITED Keyword: embedded systems, verification,
	Summary \| Full Text:PDF (1.7MB)

Towards Inferring Inter-Domain Routing Policies in ISP Networks Wei LIANG Jingping BI Zhongcheng LI Yiting XIA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2011/11/01 Vol. E94-B No. 11 pp. 3049-3056 Type of Manuscript: PAPER Category: Network Management/Operation Keyword: BGP, routing policy, verification, inference,
	Summary \| Full Text:PDF (491.9KB)

A Low Power SOC Architecture for the V2.0+EDR Bluetooth Using a Unified Verification Platform Jeonghun KIM Suki KIM Kwang-Hyun BAEK
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/09/01 Vol. E93-D No. 9 pp. 2500-2508 Type of Manuscript: PAPER Category: Computer System Keyword: Bluetooth V2.0, enhanced data rate (EDR), low-power architecture, wireless SOC, sub band codec, platform-based design, verification,
	Summary \| Full Text:PDF (598.4KB)

HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms Liang-Bi CHEN Jiun-Cheng JU Chien-Chou WANG Ing-Jer HUANG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2100-2108 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Multiple-Valued VLSI Technology Keyword: AMBA, debugging, system-on-a-chip (SoC), protocol checker, verification,
	Summary \| Full Text:PDF (1.2MB)

Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns Kenta YAMADA Toshiyuki SYO Hisao YOSHIMURA Masaru ITO Tatsuya KUNIKIYO Toshiki KANAMOTO Shigetaka KUMASHIRO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/08/01 Vol. E93-C No. 8 pp. 1349-1358 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: STI, stress, model, verification, enhancement,
	Summary \| Full Text:PDF (2.2MB)

Towards Reliable E-Government Systems with the OTS/CafeOBJ Method Weiqiang KONG Kazuhiro OGATA Kokichi FUTATSUGI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/05/01 Vol. E93-D No. 5 pp. 974-984 Type of Manuscript: Special Section PAPER (Special Section on Formal Approach) Category: Formal Specification Keyword: e-Government messaging framework, formal methods, the OTS/CafeOBJ method, falsification, verification,
	Summary \| Full Text:PDF (533KB)

Feature Interaction Verification Using Unbounded Model Checking with Interpolation Takafumi MATSUO Tatsuhiro TSUCHIYA Tohru KIKUNO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/06/01 Vol. E92-D No. 6 pp. 1250-1259 Type of Manuscript: PAPER Category: Dependable Computing Keyword: unbounded model checking, interpolation, feature interaction, verification,
	Summary \| Full Text:PDF (209.8KB)

Verification of the Security against Inference Attacks on XML Databases Kenji HASHIMOTO Kimihide SAKANO Fumikazu TAKASUKA Yasunori ISHIHARA Toru FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/05/01 Vol. E92-D No. 5 pp. 1022-1032 Type of Manuscript: Special Section PAPER (Special Section on Formal Approach) Category: Security Keyword: XML database, inference attack, security, verification,
	Summary \| Full Text:PDF (810.5KB)

Probabilistic Model Checking of the One-Dimensional Ising Model Toshifusa SEKIZAWA Tatsuhiro TSUCHIYA Koichi TAKAHASHI Tohru KIKUNO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/05/01 Vol. E92-D No. 5 pp. 1003-1011 Type of Manuscript: Special Section PAPER (Special Section on Formal Approach) Category: Model Checking Keyword: verification, probabilistic model checking, the Ising model, Discrete Time Markov Chain,
	Summary \| Full Text:PDF (705.5KB)

DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction Shigeru YAMASHITA Shin-ichi MINATO D. Michael MILLER
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3793-3802 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: quantum circuit, verification, decision diagram,
	Summary \| Full Text:PDF (482.5KB)

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems Masato INAGI Yasuhiro TAKASHIMA Yuichi NAKAMURA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3539-3547 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: FPGA prototyping, ILP, I/O pins constraint, verification, time-multiplexed I/O,
	Summary \| Full Text:PDF (308.3KB)

On Backward-Style Anonymity Verification Yoshinobu KAWABE Ken MANO Hideki SAKURADA Yasuyuki TSUKADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/09/01 Vol. E91-A No. 9 pp. 2597-2606 Type of Manuscript: PAPER Category: Cryptography and Information Security Keyword: formal methods, anonymity, software security, verification, theorem-proving,
	Summary \| Full Text:PDF (665.9KB)

A Specification Translation from Behavioral Specifications to Rewrite Specifications Masaki NAKAMURA Weiqiang KONG Kazuhiro OGATA Kokichi FUTATSUGI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/05/01 Vol. E91-D No. 5 pp. 1492-1503 Type of Manuscript: PAPER Category: Fundamentals of Software and Theory of Programs Keyword: specification translation, verification, algebraic specification, behavioral specification, rewirte specification, CafeOBJ, Maude,
	Summary \| Full Text:PDF (305.3KB)

An Adversary Model for Simulation-Based Anonymity Proof Yoshinobu KAWABE Hideki SAKURADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 pp. 1112-1120 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: formal methods, anonymity, software security, verification, theorem-proving,
	Summary \| Full Text:PDF (208KB)

An XQDD-Based Verification Method for Quantum Circuits Shiou-An WANG Chin-Yung LU I-Ming TSAI Sy-Yen KUO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/02/01 Vol. E91-A No. 2 pp. 584-594 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: quantum computing, quantum circuits, verification, decision diagram,
	Summary \| Full Text:PDF (467.8KB)

Instruction Based Synthesizable Testbench Architecture Ho-Seok CHOI Hae-Wook CHOI Sin-Chong PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/05/01 Vol. E89-C No. 5 pp. 653-657 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: verification, testbench, emulation, instruction,
	Summary \| Full Text:PDF (959.1KB)

Accelerating Verification with Reusable Testbench Jungbo SON Hae-Wook CHOI Sin-Chong PARK
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/02/01 Vol. E89-D No. 2 pp. 853-856 Type of Manuscript: LETTER Category: Dependable Computing Keyword: verification, testbench, reuse, Aptix, Celaro,
	Summary \| Full Text:PDF (423.2KB)

Verifiable Oblivious Transfer Protocol Narn-Yih LEE Chien-Chih WANG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/12/01 Vol. E88-D No. 12 pp. 2890-2892 Type of Manuscript: LETTER Category: Application Information Security Keyword: oblivious transfer, verification, zero knowledge, cryptography, same message attack,
	Summary \| Full Text:PDF (73.6KB)

Symbolic Reachability Analysis of Probabilistic Linear Hybrid Automata Yosuke MUTSUDA Takaaki KATO Satoshi YAMANE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/11/01 Vol. E88-A No. 11 pp. 2972-2981 Type of Manuscript: Special Section PAPER (Special Section on Concurrent/Hybrid Systems: Theory and Applications) Category: Keyword: verification, performance evaluation, formal specification, probabilistic hybrid automata, reachability, symbolic methods,
	Summary \| Full Text:PDF (643.6KB)

Policy Controlled System and Its Model Checking Shigeta KUNINOBU Yoshiaki TAKATA Naoya NITTA Hiroyuki SEKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1685-1696 Type of Manuscript: PAPER Category: Application Information Security Keyword: policy control, policy controlled system, verification, model checking, pushdown system,
	Summary \| Full Text:PDF (1.3MB)

Efficient Block-Level Connectivity Verification Algorithms for Embedded Memories Jin-Fu LI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3185-3192 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: system on chip, embedded memories, verification, signal misplaced fault,
	Summary \| Full Text:PDF (445.7KB)

A Comprehensive Simulation and Test Environment for Prototype VLSI Verification Kazutoshi KOBAYASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 630-636 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Verification Keyword: simulation, test, VLSI, tester, verification,
	Summary \| Full Text:PDF (1.4MB)

Study and Analysis of System LSI Design Methodologies Using C-Based Behavioral Synthesis Hidefumi KUROKAWA Hiroyuki IKEGAMI Motohide OTSUBO Kiyoshi ASAO Kazuhisa KIRIGAYA Katsuya MISU Satoshi TAKAHASHI Tetsuji KAWATSU Kouji NITTA Hiroshi RYU Kazutoshi WAKABAYASHI Minoru TOMOBE Wataru TAKAHASHI Akira MUKOUYAMA Takashi TAKENAKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/04/01 Vol. E86-A No. 4 pp. 787-798 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: C-based design, behavioral synthesis, verification, design productivity, model abstraction,
	Summary \| Full Text:PDF (2.1MB)

Symbolic Model Checking of Deadlock Free Property of Task Control Architecture Hiromi HIRAISHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1579-1586 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Verification Keyword: verification, symbolic model checking, deadlock, robot control program, concurrent process,
	Summary \| Full Text:PDF (267.5KB)

Identification Algorithm Using a Matching Score Matrix Takuji MAEDA Masahito MATSUSHITA Koichi SASAKAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/07/01 Vol. E84-D No. 7 pp. 819-824 Type of Manuscript: Special Section PAPER (Special Issue on Biometric Person Authentication) Category: Keyword: identification, verification, biometrics, fingerprint, matrix, correlation,
	Summary \| Full Text:PDF (604KB)

High Level Analysis of Clock Regions in a C++ System Description Luc RYNDERS Patrick SCHAUMONT Serge VERNALDE Ivo BOLSENS
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/20 Vol. E83-A No. 12 pp. 2631-2632 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: High-level Synthesis Keyword: clocking analysis, C++ modeling, verification, model of computation,
	Summary \| Full Text:PDF (191.2KB)

A New Verification Method Using Virtual System States for Responsive Communication Protocols and Its Application to a Broadcasting Protocol Shin'ichi NAGANO Yoshiaki KAKUDA Tohru KIKUNO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/04/20 Vol. E81-A No. 4 pp. 596-604 Type of Manuscript: Special Section PAPER (Special Section on Concurrent Systems Technology) Category: Keyword: communication protocol, responsiveness, verification, virtual system state, reachability analysis,
	Summary \| Full Text:PDF (781.3KB)

Refinement and Validation of Software Requirements Using Incremental Simulation Kyo-Chul KANG Kwan W. LEE Ji-young LEE Jounghyun (Gerard) KIM Hye-jung KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/02/20 Vol. E81-D No. 2 pp. 171-182 Type of Manuscript: PAPER Category: Sofware System Keyword: real-time systems, requirements specification, requirements analysis, specification execution, statechart, validation, verification, incremental development,
	Summary \| Full Text:PDF (1.2MB)

Time-Action Alternating Model for Timed Processes and Its Symbolic Verification of Bisimulation Equivalence Akio NAKATA Teruo HIGASHINO Kenichi TANIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/02/20 Vol. E80-A No. 2 pp. 400-406 Type of Manuscript: PAPER Category: Concurrent Systems Keyword: timed bisimulation equivalence, verification, symbolic bisimulation, A-TSLTS, most general boolean,
	Summary \| Full Text:PDF (576KB)

On Verification of Token Self-Cleanness of Data-Flow Program Nets Qi-Wei GE Kenji ONAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/06/20 Vol. E79-A No. 6 pp. 812-817 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1995 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '95)) Category: Keyword: data-flow program, program net, token selfcleanness, verification,
	Summary \| Full Text:PDF (571.4KB)

A Flexible Verifier of Temporal Properties for LOTOS Kaoru TAKAHASHI Yoshiaki TOKITA Takehisa TANAKA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/01/20 Vol. E79-D No. 1 pp. 8-21 Type of Manuscript: PAPER Category: Sofware System Keyword: specification, verification, protocol, LOTOS, software tool,
	Summary \| Full Text:PDF (1MB)

Verification and Refinement for System Requirements Kukhwan SONG Atushi TOGASHI Norio SHIRATORI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/11/20 Vol. E78-A No. 11 pp. 1468-1478 Type of Manuscript: Special Section PAPER (Special Section on Net Theory and Its Applications to Discrete Event System Design) Category: Keyword: system requirement, formal specification, state transition, Petri Net, verification, refinement,
	Summary \| Full Text:PDF (875KB)

Practical Program Validation for State-Based Reactive Concurrent Systems--Harmonization of Simulation and Verification-- Naoshi UCHIHIRA Hideji KAWATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/11/20 Vol. E78-A No. 11 pp. 1487-1497 Type of Manuscript: Special Section PAPER (Special Section on Net Theory and Its Applications to Discrete Event System Design) Category: Keyword: state transition system, reactive concurrent system, exhaustive simulation, verification, state space analysis, partial order method,
	Summary \| Full Text:PDF (896.7KB)

Hierarchical Analysis System for VLSI Power Supply Network Takeshi YOSHITOME
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/20 Vol. E76-A No. 10 pp. 1659-1665 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: LSI layout, verification, power supply network, voltage drop,
	Summary \| Full Text:PDF (515.2KB)

Critical Slice-Based Fault Localization for Any Type of Error Takao SHIMOMURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/06/20 Vol. E76-D No. 6 pp. 656-667 Type of Manuscript: PAPER Category: Software Systems Keyword: algorithmic debugging, errors, failures, faults, slices, verification,
	Summary \| Full Text:PDF (943.2KB)

On the Specification for VLSI Systolic Arrays Fuyau LIN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/04/20 Vol. E76-A No. 4 pp. 496-506 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: formal specification, Z, systolic architectures, verification,
	Summary \| Full Text:PDF (707.6KB)

A Spoken Dialog System with Verification and Clarification Queries Mikio YAMAMOTO Satoshi KOBAYASHI Yuji MORIYA Seiichi NAKAGAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/01/20 Vol. E76-D No. 1 pp. 84-94 Type of Manuscript: Special Section PAPER (Special Issue on Speech and Discourse Processing in Dialogue Systems) Category: Keyword: natural language processing, speech recognition, dialog system, verification, clarification,
	Summary \| Full Text:PDF (939.8KB)

Verification of Register Transfer Level (RTL) Designs Alberto Palacios PAWLOVSKY Sachio NAITO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/11/20 Vol. E75-D No. 6 pp. 785-791 Type of Manuscript: Special Section PAPER (Special Issue on Pacific Rim International Symposium on Fault Tolerant Systems) Category: Keyword: fault analysis, testing, verification, hardware description languages, regular expressions, directed graphs,
	Summary \| Full Text:PDF (635.4KB)

Verification of Switching Software by Knowledge Processing Technology Mitsuaki KAKEMIZU Yasuo IWAMI Yoshiharu SATO Shimmi HATTORI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1992/10/20 Vol. E75-B No. 10 pp. 1008-1014 Type of Manuscript: Special Section PAPER (Special Issue on Communication Software Technologies) Category: Keyword: verification, knowledge base, object-oriented, simulation, switching software,
	Summary \| Full Text:PDF (588.2KB)

A Method of Composing Communication Protocols with Priority Service Masahiro HIGUCHI Hiroyuki SEKI Tadao KASAMI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1992/10/20 Vol. E75-B No. 10 pp. 1032-1042 Type of Manuscript: Special Section PAPER (Special Issue on Communication Software Technologies) Category: Keyword: communication protocol, communicating sequential machines, safety property, verification, reachability analysis,
	Summary \| Full Text:PDF (878.2KB)

Formal Specification and Verification of ISDN Services in LOTOS Keiichirou YAMANO Dusan JOKANOVIC Tsuyoshi ANDO Masataka OHTA Kaoru TAKAHASHI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1992/08/20 Vol. E75-B No. 8 pp. 715-722 Type of Manuscript: Special Section PAPER (Special Issue on the 4th Japan-Korea Joint Conference on Communications, Networks, Switching Systems and Satellite Communications (4th JC-CNSS)) Category: Keyword: LOTOS, specification, verification, switching software,
	Summary \| Full Text:PDF (659.6KB)