Keyword : variable line-size


Reducing On-Chip DRAM Energy via Data Transfer Size Optimization
Takatsugu ONO Koji INOUE Kazuaki MURAKAMI Kenji YOSHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4 ; pp. 433-443
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
low powervariable line-sizeon-chip DRAMhigh bandwidthembedded systems
 Summary | Full Text:PDF(497.8KB)

A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11 ; pp. 1716-1723
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
cachelow powervariable line-sizemerged DRAM/logic LSIshigh bandwidth
 Summary | Full Text:PDF(1001.2KB)

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Vol. E83-D  No. 5 ; pp. 1048-1057
Type of Manuscript:  PAPER
Category: Computer System Element
Keyword: 
cachevariable line-sizemerged DRAM/logic LSIshigh bandwidth
 Summary | Full Text:PDF(1015.7KB)