Keyword : validation

Verification of Spark-Resistance Formulae for Micro-Gap ESD
Yoshinori TAKA  Osamu FUJIWARA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/07/01
Vol. E93-B  No. 7  pp. 1801-1806
Type of Manuscript: Special Section PAPER (Special Section on Advanced Electromagnetic Compatibility Technology in Conjunction with Main Topics of EMC'09/Kyoto)
Category: ESD and Transients
Keyword: 
micro-gap ESDs,  spark-resistance formulae,  Rompe-Weizel,  Toepler,  validation, 
  Summary |  Full Text:PDF (4.1MB)
Formal Verification of an Intrusion-Tolerant Group Membership Protocol
HariGovind V. RAMASAMY  Michel CUKIER  William H. SANDERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12  pp. 2612-2622
Type of Manuscript: Special Section PAPER (Special Issue on Dependable Computing)
Category: Verification and Dependability Analysis
Keyword: 
intrusion tolerance,  group communication systems,  validation,  formal methods, 
  Summary |  Full Text:PDF (537.5KB)
Refinement and Validation of Software Requirements Using Incremental Simulation
Kyo-Chul KANG  Kwan W. LEE  Ji-young LEE  Jounghyun (Gerard) KIM  Hye-jung KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/02/20
Vol. E81-D  No. 2  pp. 171-182
Type of Manuscript: PAPER
Category: Sofware System
Keyword: 
real-time systems,  requirements specification,  requirements analysis,  specification execution,  statechart,  validation,  verification,  incremental development, 
  Summary |  Full Text:PDF (1.2MB)
Statechart Methodology for the Design, Validation, and Synthesis of Large Scale Asynchronous Systems
Rakefet KOL  Ran GINOSAR  Goel SAMUEL 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/03/20
Vol. E80-D  No. 3  pp. 308-314
Type of Manuscript: Special Section PAPER (Special Issue on Asynchronous Circuit and System Design)
Category: Specification Description
Keyword: 
asynchronous logic design,  statechart,  validation,  synthesis, 
  Summary |  Full Text:PDF (573.9KB)
Validation of UDL/I Test Suites and UDL/I Simulation/Synthesis Environment
Hiroyuki KANBARA  Satoshi YOKOTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/20
Vol. E78-A  No. 12  pp. 1749-1754
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware description language,  test suites,  validation,  CAD, 
  Summary |  Full Text:PDF (434.5KB)