Keyword : timing verification


Multi-Cycle Path Detection Based on Propositional Satisfiability with CNF Simplification Using Adaptive Variable Insertion
Kazuhiro NAKAMURA Shinji MARUOKA Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2600-2607
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
timing verificationmaximum delay analysismulti-cycle pathspropositional satisfiability
 Summary | Full Text:PDF(365KB)

Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis
Kazuhiro NAKAMURA Shinji KIMURA Kazuyoshi TAKAGI Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2515-2520
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Optimization
Keyword: 
timing verificationmaximum delay analysismultiple clock operationfalse path
 Summary | Full Text:PDF(546.5KB)

Prciseness of Discrete Time Verification
Shinji KIMURA Shunsuke TSUBOTA Hiromasa HANEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1755-1759
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
timing verificationdiscrete time analysistiming simulationunit time selection
 Summary | Full Text:PDF(390.9KB)

Hierarchical Timing Analyzer for Multiple Phase Clocked Designs
Hiromi ISHIKAWA Masanori IMAI Junko KOBARA Shinichi MURAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/12/25
Vol. E75-A  No. 12 ; pp. 1732-1735
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Fall Conference)
Category: 
Keyword: 
timing analysistiming verificationstatic timing analysishierarchical timing analysissynchronous designCAD
 Summary | Full Text:PDF(288.5KB)

Timing Verification of Logic Circuits with Combined Delay Model
Shinji KIMURA Shigemi KASHIMA Hiromasa HANEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1230-1238
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
timing verificationcomputer aided designlogic simulation
 Summary | Full Text:PDF(741.8KB)

Coded Time-Symbolic Simulation for Timing Verification of Logic Circuits
Nagisa ISHIURA Yutaka DEGUCHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1247-1254
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic circuitstiming verificationsymbolic simulationBoolean function manipulation
 Summary | Full Text:PDF(636.9KB)