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Keyword : threshold voltage

Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs Tomoko MIZUTANI Anil KUMAR Toshiro HIRAMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/05/01 Vol. E96-C No. 5 pp. 630-633 Type of Manuscript: BRIEF PAPER Category: Keyword: variability, MOS transistor, threshold voltage, DIBL, normal distribution, Gumbel distribution,
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Study on Threshold Voltage Control of Tunnel Field-Effect Transistors Using V_T-Control Doping Region Hyungjin KIM Min-Chul SUN Hyun Woo KIM Sang Wan KIM Garam KIM Byung-Gook PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/05/01 Vol. E95-C No. 5 pp. 820-825 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: Tunnel Field-Effect Transistors, threshold voltage, V_T-control doping region,
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On-Chip Temperature Compensation Active Bias Circuit Having Tunable Temperature Slope for GaAs FET MMIC PA Shintaro SHINJO Kazutomi MORI Tomokazu OGOMI Yoshihiro TSUKAHARA Mitsuhiro SHIMOZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/10/01 Vol. E94-C No. 10 pp. 1498-1507 Type of Manuscript: Special Section PAPER (Special Section on Microwave and Millimeter-Wave Technology) Category: Active Devices and Circuits Keyword: temperature compensation, MMIC power amplifiers, GaAs FET, threshold voltage,
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A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage Using VCDL and Time-to-Digital Converter Jae-seung LEE Jae-Yoon SIM Hong June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/08/01 Vol. E93-C No. 8 pp. 1333-1337 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: on-chip variation monitoring, threshold voltage, time-to-digital converter (TDC), voltage controlled delay line (VCDL),
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Analysis of Passivation-Film-Induced Stress Effects on Electrical Properties in AlGaN/GaN HEMTs Naoteru SHIGEKAWA Suehiro SUGITANI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/08/01 Vol. E93-C No. 8 pp. 1212-1217 Type of Manuscript: Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM 2009) Category: GaN-based Devices Keyword: GaN, HEMT, threshold voltage, piezoelectric effects, film stress,
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Control of P3HT-FET Characteristics by Post-Treatments Masaaki IIZUKA Hiroshi YAMAUCHI Kazuhiro KUDO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/12/01 Vol. E91-C No. 12 pp. 1848-1851 Type of Manuscript: Special Section PAPER (Special Section on The Forefront of 21st Century Organic Molecular Electronics) Category: Transistors Keyword: organic field-effect transistor, P3HT, threshold voltage, post-treatment, thermal treatment,
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An Ultra Low-Voltage Ultra Low-Power CMOS Threshold Voltage Reference Luis H.C. FERREIRA Tales C. PIMENTA Robson L. MORENO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 2044-2050 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: threshold voltage, voltage reference, ultra low-power, ultra low-voltage,
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Enhancement-Mode AlGaN/GaN HEMTs with Low On-Resistance and Low Knee-Voltage Yong CAI Yugang ZHOU Kei May LAU Kevin J. CHEN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/07/01 Vol. E89-C No. 7 pp. 1025-1030 Type of Manuscript: Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM2005) Category: GaN-Based Devices Keyword: enhancement mode, AlGaN/GaN, HEMT, fluoride, plasma treatment, threshold voltage,
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Temperature and Illumination Dependence of AlGaN/GaN HFET Threshold Voltage Masaya OKADA Ryohei TAKAKI Daigo KIKUTA Jin-Ping AO Yasuo OHNO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/07/01 Vol. E89-C No. 7 pp. 1042-1046 Type of Manuscript: Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM2005) Category: GaN-Based Devices Keyword: AlGaN/GaN HFETs, threshold voltage, temperature coefficient, illumination, buffer layer,
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Threshold Voltage Mismatch of FD-SOI MOSFETs Yoshiyuki SHIMIZU Toshimasa MATSUOKA Kenji TANIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/06/01 Vol. E87-C No. 6 pp. 1013-1014 Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit and Device Technologies) Category: Keyword: threshold voltage, FD-SOI, floating body effect, DIBL,
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A New Method to Extract MOSFET Threshold Voltage, Effective Channel Length, and Channel Mobility Using S-parameter Measurement Han-Yu CHEN Kun-Ming CHEN Guo-Wei HUANG Chun-Yen CHANG Tiao-Yuan HUANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/05/01 Vol. E87-C No. 5 pp. 726-732 Type of Manuscript: Special Section PAPER (Special Section on Advances in Characterization and Measurement Technologies for Microwave and Millimeter-Wave Materials, Devices and Circuits) Category: Active Devices and Circuits Keyword: threshold voltage, effective channel length, channel mobility, S-parameter, automatic measurement,
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A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor Toshihiro HATTORI Kenji OGURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 520-526 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: threshold voltage, low power, dual-Vth, physical synthesis,
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Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control Akira MOCHIZUKI Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 582-588 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: differential-pair circuit, substrate bias control, dynamic power dissipation, threshold voltage, low-power VLSI, leakage current,
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A Realization of a Common-Source FG-MOSFET with a Simple Electronic V_th Adjustment Almost Irrelevant to the Amount of the Pre-stored Charge on the Floating Gate Takahiro INOUE Eizo ICHIHARA Toshitaka YAMAKAWA Akio TSUNEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/03/01 Vol. E87-A No. 3 pp. 753-756 Type of Manuscript: LETTER Category: Analog Signal Processing Keyword: floating-gate MOSFET, threshold voltage, V_th adjustment,
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A New Non-Pair Diffusion Based Dopant Pile-up Model for Process Designers and Its Prediction Accuracy Hirokazu HAYASHI Noriyuki MIURA Hirotaka KOMATSUBARA Marie MOCHIZUKI Koichi FUKUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/03/01 Vol. E86-C No. 3 pp. 453-458 Type of Manuscript: Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02)) Category: Keyword: RSCE, simple model, dopant pile-up, threshold voltage,
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An Equivalent MOSFET Cell Using Adaptively Biased Source-Coupled Pair Hiroki SATO Akira HYOGO Keitaro SEKINE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/02/01 Vol. E86-A No. 2 pp. 357-363 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: MOS analog circuit, threshold voltage, source-coupled pair, adaptively bias technique,
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A Simplified Dopant Pile-Up Model for Process Simulators Hirokazu HAYASHI Noriyuki MIURA Hirotaka KOMATSUBARA Marie MOCHIZUKI Koichi FUKUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/12/01 Vol. E85-C No. 12 pp. 2117-2122 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: RSCE, simple model, dopant pile-up, threshold voltage,
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A 100 nm Node CMOS Technology for System-on-a-Chip Applications Kiyotaka IMAI Atsuki ONO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/05/01 Vol. E85-C No. 5 pp. 1057-1063 Type of Manuscript: INVITED PAPER (Special Issue on Advanced Sub-0.1 µm CMOS Devices) Category: Keyword: CMOS, threshold voltage, gate leakage current, oxynitride,
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A Simplified Process Modeling for Reverse Short Channel Effect of Threshold Voltage of MOSFET Hirokazu HAYASHI Noriyuki MIURA Hirotaka KOMATSUBARA Koichi FUKUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/09/01 Vol. E84-C No. 9 pp. 1234-1239 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: RSCE, simple model, dopant pile-up, threshold voltage,
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Low Power CMOS Design Challenges Tadahiro KURODA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/08/01 Vol. E84-C No. 8 pp. 1021-1028 Type of Manuscript: INVITED PAPER (Special Issue on Silicon Nanodevices) Category: Keyword: low power CMOS design, low voltage, threshold voltage, subthreshold leakage current, downsizing,
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Fabrication and Characterization of 1T2C-Type Ferroelectric Memory Cell Satoru OGASAWARA Sung-Min YOON Hiroshi ISHIWARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/06/01 Vol. E84-C No. 6 pp. 771-776 Type of Manuscript: Special Section PAPER (Special Issue on Nonvolatile Memories) Category: FeRAMs Keyword: ferroelectric-gate FET, retention, 1T2C, memory window, threshold voltage,
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Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2-V Power Supply CMOS Naoki KATO Yohei AKITA Mitsuru HIRAKI Takeo YAMASHITA Teruhisa SHIMIZU Fuyuhiko MAKI Kazuo YANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/11/20 Vol. E83-C No. 11 pp. 1747-1754 Type of Manuscript: Special Section PAPER (Special Issue on Low-power LSIs and Technologies) Category: Keyword: CMOS, threshold voltage, leakage current, low power,
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Variable Threshold-Voltage CMOS Technology Tadahiro KURODA Tetsuya FUJITA Fumitoshi HATORI Takayasu SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/11/20 Vol. E83-C No. 11 pp. 1705-1715 Type of Manuscript: INVITED PAPER (Special Issue on Low-power LSIs and Technologies) Category: Keyword: low power CMOS design, low voltage, threshold voltage, substrate bias,
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Inverse Modeling and Its Application to MOSFET Channel Profile Extraction Hirokazu HAYASHI Hideaki MATSUHASHI Koichi FUKUDA Kenji NISHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/06/20 Vol. E82-C No. 6 pp. 862-869 Type of Manuscript: INVITED PAPER (Special Issue on TCAD for Semiconductor Industries) Category: Keyword: inverse modeling, doping profile extraction, MOSFET, threshold voltage,
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Neuron-MOSV_T Cancellation Circuit and Its Application to a Low-Power and High-Swing Cascode Current Mirror Koichi TANNO Jing SHEN Okihiko ISHIZUKA Zheng TANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/01/20 Vol. E81-A No. 1 pp. 110-116 Type of Manuscript: PAPER Category: Analog Signal Processing Keyword: neuron-MOS transistor, threshold voltage, CMOS analog circuit, circuit theory and design, integrated circuit,
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An Accurate Model of Fully-Depleted Surrounding Gate Transistor (FD-SGT) Tetsuo ENDOH Tairiku NAKAMURA Fujio MASUOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/20 Vol. E80-C No. 7 pp. 905-910 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Novel Structure Devices Keyword: SGT, FD-SGT, current-voltage characteristics, threshold voltage,
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An Analytic Steady-State Current-Voltage Characteristics of Short Channel Fully-Depleted Surrounding Gate Transistor (FD-SGT) Tetsuo ENDOH Tairiku NAKAMURA Fujio MASUOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/20 Vol. E80-C No. 7 pp. 911-917 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Novel Structure Devices Keyword: SGT, FD-SGT, current-voltage characteristics, threshold voltage, short channel effect,
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1: n² MOS Cascode Circuits and Their Applications Koichi TANNO Okihiko ISHIZUKA Zheng TANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/12/20 Vol. E79-A No. 12 pp. 2159-2165 Type of Manuscript: PAPER Category: Analog Signal Processing Keyword: MOS analog circuit, MOS LSI, circuit theory and design, integrated circuit, threshold voltage,
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Design Methodology of Deep Submicron CMOS Devices for 1 V Operation Hisato OYAMATSU Masaaki KINUGAWA Masakazu KAKUMU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/20 Vol. E79-C No. 12 pp. 1720-1725 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: low voltage, low power dissipation, threshold voltage, CMOS,
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A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs Tsuneo INABA Daisaburo TAKASHIMA Yukihito OOWAKI Tohru OZAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI Hiroyuki TANGO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/20 Vol. E79-C No. 12 pp. 1699-1706 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: DRAM, power dissipation, reliability, bit-line, wordline, small swing, threshold voltage, sense amplifier, memory cell,
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Threshold Voltage Control Using Floating Back Gate for Ultra-Thin-Film SOI CMOS Seiji FUJINO Kazuhiro TSURUTA Akiyoshi ASAI Tadashi HATTORI Yoshihiro HAMAKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/12/20 Vol. E78-C No. 12 pp. 1773-1778 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: SOI, threshold voltage, wafer direct bonding, floating back gate, electric charge injection, ring oscillator,
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Design of a Novel MOS V_T Extractor Circuit Koichi TANNO Okihiko ISHIZUKA Zhen TANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/09/20 Vol. E78-C No. 9 pp. 1306-1310 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: MOS analog circuit, threshold voltage, MOS LSI, circuit theory and design, integrated circuit,
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High-Speed and Low-Power n⁺-p⁺ Double-Gate SOI CMOS Kunihiro SUZUKI Tetsu TANAKA Yoshiharu TOSAKA Hiroshi HORIE Toshihiro SUGII
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/20 Vol. E78-C No. 4 pp. 360-367 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: Device Technology Keyword: MOSFET, SOI, double-gate, high-speed, low-power, threshold voltage,
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A Proposal of New Multiple-Valued Mask-ROM Design Yasushi KUBOTA Shinji TOYOYAMA Yoji KANIE Shuhei TSUCHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/04/20 Vol. E77-C No. 4 pp. 601-607 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: semiconductor devices, mask-ROM, multiple-value, threshold voltage, channel length,
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