Keyword : test generation


A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation
Toshinori HOSOKAWA Atsushi HIRAI Yukari YAMAUCHI Masayuki ARAI 
Publication:   
Publication Date: 2017/09/01
Vol. E100-D  No. 9 ; pp. 2118-2125
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
low powertest generationcapture safe test vectorstest vector synthesisunsafe faults
 Summary | Full Text:PDF(1.4MB)

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment
Yoshinobu HIGAMI Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/06/01
Vol. E96-D  No. 6 ; pp. 1323-1331
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test generationfault simulationclock linedelay fault
 Summary | Full Text:PDF(595KB)

Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool
Yoshinobu HIGAMI Satoshi OHNO Hironori YAMAOKA Hiroshi TAKAHASHI Yoshihiro SHIMIZU Takashi AIKYO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/04/01
Vol. E95-D  No. 4 ; pp. 1093-1100
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
fault diagnosistest generationtransition faultsstuck-at ATPG
 Summary | Full Text:PDF(502.5KB)

A Study of Capture-Safe Test Generation Flow for At-Speed Testing
Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA Yuta YAMATO Atsushi TAKASHIMA Hiroshi FURUKAWA Kenji NODA Hideaki ITO Kazumi HATAYAMA Takashi AIKYO Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7 ; pp. 1309-1318
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
at-speed scan testingtest generationX-bit identificationX-fillingcapture-safety checking
 Summary | Full Text:PDF(3.5MB)

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3128-3135
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
test generationtransistor defectsstuck-at testsdefect coverage
 Summary | Full Text:PDF(299.6KB)

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3506-3513
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
fault simulationtest generationstuck-open faultsstuck-at testsdefect coverage
 Summary | Full Text:PDF(283.9KB)

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 690-699
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Defect-Based Testing
Keyword: 
transistor shortfault simulationtest generationstuck-at test tool
 Summary | Full Text:PDF(346.3KB)

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability
Masato NAKAZATO Satoshi OHTAKE Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1 ; pp. 296-305
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
sequential circuittest generationsynthesis for testabilityfinite state machinetest knowledge
 Summary | Full Text:PDF(641.6KB)

On Finding Don't Cares in Test Sequences for Sequential Circuits
Yoshinobu HIGAMI Seiji KAJIHARA Irith POMERANZ Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/11/01
Vol. E89-D  No. 11 ; pp. 2748-2755
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test generationdon't care valuesequential circuitstuck-at fault
 Summary | Full Text:PDF(195KB)

Classification of Sequential Circuits Based on τk Notation and Its Applications
Chia Yee OOI Thomas CLOUQUEUR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/12/01
Vol. E88-D  No. 12 ; pp. 2738-2747
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
test generationeasily testable sequential circuitscomplexitydesign for testabilitysynthesis for testability
 Summary | Full Text:PDF(391.4KB)

Generation of Test Sequences with Low Power Dissipation for Sequential Circuits
Yoshinobu HIGAMI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 530-536
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Test Generation and Compaction
Keyword: 
LSI testingsequential circuittest generationlow power dissipationstuck-at fault
 Summary | Full Text:PDF(176KB)

Don't Care Identification and Statistical Encoding for Test Data Compression
Seiji KAJIHARA Kenjiro TANIGUCHI Kohei MIYASE Irith POMERANZ Sudhakar M. REDDY 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 544-550
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Test Generation and Compaction
Keyword: 
test compressiondon't care identificationHuffman's algorithmtest generation
 Summary | Full Text:PDF(377.8KB)

An Alternative Test Generation for Path Delay Faults by Using Ni-Detection Test Sets
Hiroshi TAKAHASHI Kewal K. SALUJA Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12 ; pp. 2650-2658
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
test generationpath delay faults N-propagation test-pair setcombinational circuits
 Summary | Full Text:PDF(587.1KB)

A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG
Hideyuki ICHIHARA Tomoo INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3072-3078
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
test generationacyclic sequential circuitsstuck-at faultpartial scanmultiple fault
 Summary | Full Text:PDF(383.3KB)

High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model
Michinobu NAKAO Yoshikazu KIYOSHIGE Yasuo SATO Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1506-1514
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
delay testingpath selectionfault simulationtest generationpath-status graph
 Summary | Full Text:PDF(322.4KB)

Test Generation for Test Compression Based on Statistical Coding
Hideyuki ICHIHARA Atsuhiro OGAWA Tomoo INOUE Akio TAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1466-1473
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test Generation and Modification
Keyword: 
VLSI testtest compressionstatistical codetest generationautomatic test equipment
 Summary | Full Text:PDF(298.2KB)

Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits
Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1474-1482
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test Generation and Modification
Keyword: 
test generationtest planscompacted test plan tablestest plan compatibility graphRTL data path
 Summary | Full Text:PDF(1.2MB)

On Processing Order for Obtaining Implication Relations in Static Learning
Hideyuki ICHIHARA Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Vol. E83-D  No. 10 ; pp. 1908-1911
Type of Manuscript:  LETTER
Category: Fault Tolerance
Keyword: 
test generationimplicationstatic learning
 Summary | Full Text:PDF(179.4KB)

A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits
Hiroshi TAKAHASHI Kwame Osei BOATENG Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/11/25
Vol. E82-D  No. 11 ; pp. 1466-1473
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
combinational circuitmarginal chipgate delay faulttest generationtest with linearity property
 Summary | Full Text:PDF(598KB)

Test Generation for Sequential Circuits under IDDQ Testing
Toshiyuki MAEDA Yoshinobu HIGAMI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 689-696
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: IDDQ Testing
Keyword: 
sequential circuittest generationIDDQ testingbridging fault
 Summary | Full Text:PDF(707.5KB)

Performance Analysis of Parallel Test Generation for Combinational Circuits
Tomoo INOUE Takaharu FUJII Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/09/25
Vol. E79-D  No. 9 ; pp. 1257-1265
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
test generationparallel processingperformance analysisinterprocessor communicationspeedup
 Summary | Full Text:PDF(723KB)

On the Effect of Scheduling in Test Generation
Tomoo INOUE Hironori MAEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8 ; pp. 1190-1197
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
test generationtest generation schedulefault orderingfault dominancecost of testing
 Summary | Full Text:PDF(654.7KB)

Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis
Seiji KAJIHARA Rikiya NISHIGAYA Tetsuji SUMIOKA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 811-816
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
test generationmultiple stuck-at faultvector pair analysiscombinational circuit
 Summary | Full Text:PDF(593KB)

A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects
Xiangqiu YU Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 822-829
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
test generationcombinational circuitsredundant faultsdelay effectextended seven-valued calculus
 Summary | Full Text:PDF(657.2KB)

A Reduced Scan Shift Method for Sequential Circuit Testing
Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2010-2016
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
sequential circuittest generationdesign for testabilityscan circuitreduced scan shift
 Summary | Full Text:PDF(625.9KB)

Stuck–Open Fault Detection in CMOS Circuits Using Single Test Patterns
Enrico MACII Qing XU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11 ; pp. 1977-1979
Type of Manuscript:  LETTER
Category: Computer Aided Design (CAD)
Keyword: 
CMOS circuitstuck–open faulttest generation
 Summary | Full Text:PDF(185.7KB)

Compact Test Sequences for Scan-Based Sequential Circuits
Hiroyuki HIGUCHI Kiyoharu HAMAGUCHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1676-1683
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
test generationscan designtest application timeboolean function manipulation
 Summary | Full Text:PDF(688KB)

Compaction of Test Sets for Combinational Circuits Based on Symbolic Fault Simulation
Hiroyuki HIGUCHI Nagisa ISHIURA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1121-1127
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Test
Keyword: 
test generationcombinational circuitscompact test setsbinary decision diagrams
 Summary | Full Text:PDF(661.1KB)

A Method of Generating Tests for Combinational Circuits with Multiple Faults
Hiroshi TAKAHASHI Nobukage IUCHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/07/25
Vol. E75-D  No. 4 ; pp. 569-576
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
multiple faultscombinational circuitstest generationrobust tests
 Summary | Full Text:PDF(641KB)