Keyword : technology mapping


SLM: A Scalable Logic Module Architecture with Less Configuration Memory
Motoki AMAGASAKI Ryo ARAKI Masahiro IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2500-2506
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAscalable logic moduletechnology mapping
 Summary | Full Text:PDF(736.9KB)

Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1374-1380
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
logic synthesistechnology mappingFPGASAT
 Summary | Full Text:PDF(223.5KB)

Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework
Junki KAWAGUCHI Hayato MASHIKO Yukihide KOHIRA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1366-1373
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
general-synchronous frameworktechnology mappinginteger linear programming
 Summary | Full Text:PDF(753.4KB)

Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs
Taiga TAKATA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3268-3275
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
FPGAtechnology mappingcut enumeration
 Summary | Full Text:PDF(340.2KB)

Technology Mapping Technique for Increasing Throughput of Character Projection Lithography
Makoto SUGIHARA Kenta NAKAMURA Yusuke MATSUNAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5 ; pp. 1012-1020
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Lithography-Related Techniques
Keyword: 
maskless lithographycharacter projectionvariable-shaped beamtechnology mappingthroughput
 Summary | Full Text:PDF(715.6KB)

Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3443-3450
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesisBoolean matchingcell-library bindingtechnology mappingcanonical form
 Summary | Full Text:PDF(326.9KB)

Fast Boolean Matching under Permutation by Efficient Computation of Canonical Form
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3134-3140
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
Boolean matchingtechnology mappingvariable permutationP-equivalence
 Summary | Full Text:PDF(691.5KB)

A Routability Driven Technology Mapping Algorithm for LUT Based FPGA Designs
Chi-Chou KAO Yen-Tai LAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2690-2696
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: FPGA Systhesis
Keyword: 
technology mappingroutabilitymin-cutfield programmable gate array (FPGA)
 Summary | Full Text:PDF(1.7MB)

Timing Driven Gate Duplication in Technology Independent Phase
Ankur SRIVASTAVA Chunhong CHEN Majid SARRAFZADEH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2673-2680
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
gate duplicationlogic synthesisdelay optimizationtechnology mapping
 Summary | Full Text:PDF(431.5KB)

Array-Based Mapping Algorithm of Logic Functions into Plastic Cell Architecture
Tomonori IZUMI Ryuji KAN Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2538-2544
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
plastic cell architecturereconfigurable logictechnology mappinglayout
 Summary | Full Text:PDF(624.1KB)

Delay-Optimal Technology Mapping for Hard-Wired Non-Homogeneous FPGAs
Hsien-Ho CHUANG Jing-Yang JOU C. Bernard SHUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2545-2551
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Performance Optimization
Keyword: 
technology mappingFPGAhard-wirednon-homogeneousXC4000
 Summary | Full Text:PDF(323.3KB)

A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs
Nozomu TOGAWA Koji ARA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A  No. 3 ; pp. 473-482
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
technology mappinglogic-blocklookup tablelogic depth
 Summary | Full Text:PDF(447.7KB)

Computational Complexity Analysis of Set-Bin-Packing Problem
Tomonori IZUMI Toshihiko YOKOMARU Atsushi TAKAHASHI Yoji KAJITANI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/05/25
Vol. E81-A  No. 5 ; pp. 842-849
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
bin-packingcomplexitytechnology mappingFPGA
 Summary | Full Text:PDF(682.7KB)

The Controlling Value Boolean Matching
Ricardo FERREIRA Anne-Marie TRULLEMANS Qinhai ZHANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1749-1755
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Boolean matchingobservabilitytechnology mappingsignatures
 Summary | Full Text:PDF(552.3KB)

Path Mapping: Delay Estimation for Technology Independent Synthesis
Yutaka TAMIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1782-1788
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
technology independent synthesistechnology mappingdelay estimation
 Summary | Full Text:PDF(498.3KB)

An Efficient FPGA Technology Mapping Tightly Coupled with Logic Minimization
Kang YI Seong Yong OHM Chu Shik JHON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1807-1812
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesistechnology mappinglogic minimizationBoolean networkfield-programmable gate array
 Summary | Full Text:PDF(534.1KB)

Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers
Jordi CORTADELLA Michael KISHINEVSKY Alex KONDRATYEV Luciano LAVAGNO Alexandre YAKOVLEV 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/03/25
Vol. E80-D  No. 3 ; pp. 315-325
Type of Manuscript:  Special Section PAPER (Special Issue on Asynchronous Circuit and System Design)
Category: Synthesis
Keyword: 
asynchronous circuitspeed independencetechnology mappingPetri netevent insertion
 Summary | Full Text:PDF(877.9KB)

Technology Mapping for FPGAs with Composite Logic Block Architectures
Hsien-Ho CHUANG C. Bernard SHUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10 ; pp. 1396-1404
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
technology mappingFPGAsubject graphpattern graph
 Summary | Full Text:PDF(730.8KB)

A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3 ; pp. 321-329
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
FPGAtechnology mappinglayoutpath delayperformance optimization
 Summary | Full Text:PDF(714.2KB)

Phase Optimization in Technology Mapping
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1735-1741
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic synthesistechnology mappingphase optimizationbinary decision diagrams
 Summary | Full Text:PDF(514.1KB)

A New Algorithm for Boolean Matching Utilizing Structural Information
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 219-223
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesistechnology mappingBoolean matchingbinary decision diagrams
 Summary | Full Text:PDF(380.7KB)

Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2028-2038
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAlook up tabletechnology mappinglayout designplacementglobal routing
 Summary | Full Text:PDF(929.2KB)