Keyword : system-on-chip


Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs
Chizu MATSUMOTO  Yuichi HAMAMURA  Michinobu NAKAO  Kaname YAMASAKI  Yoshikazu SAITO  Shun'ichi KANEKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/01/01
Vol. E96-C  No. 1  pp. 108-114
Type of Manuscript: PAPER
Category: Semiconductor Materials and Devices
Keyword: 
random access memorysystem-on-chipredundancyfuse
  Summary |  Full Text:PDF (1.5MB)

Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation
Hasitha Muthumala WAIDYASOORIYA  Daisuke OKUMURA  Masanori HARIYAMA  Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12  pp. 2570-2580
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
heterogeneous multi-core processortask-allocationsystem-on-chip
  Summary |  Full Text:PDF (1.3MB)

Performance and Power Modeling of On-Chip Bus System for a Complex SoC
Hyun LEE  Je-Hoon LEE  Kyoung-Rok CHO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/10/01
Vol. E93-C  No. 10  pp. 1525-1535
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
on-chip networkperformance modelingpower estimationarchitecture level modelingsystem-on-chip
  Summary |  Full Text:PDF (958.4KB)

Study-Based Error Recovery Scheme for Networks-on-Chip
Depeng JIN  Shijun LIN  Li SU  Lieguang ZENG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/11/01
Vol. E92-D  No. 11  pp. 2272-2274
Type of Manuscript: LETTER
Category: VLSI Systems
Keyword: 
network-on-chipsystem-on-chiperror recovery
  Summary |  Full Text:PDF (182.3KB)

Pre-Allocation Based Flow Control Scheme for Networks-On-Chip
Shijun LIN  Li SU  Haibo SU  Depeng JIN  Lieguang ZENG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/03/01
Vol. E92-D  No. 3  pp. 538-540
Type of Manuscript: LETTER
Category: VLSI Systems
Keyword: 
network-on-chipsystem-on-chipflow control
  Summary |  Full Text:PDF (124.6KB)

A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs
Hong-Ming SHIEH  Jin-Fu LI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10  pp. 2428-2434
Type of Manuscript: PAPER
Category: Dependable Computing
Keyword: 
system-on-chiptestcompressionmulti-code compressiondecompression
  Summary |  Full Text:PDF (560.7KB)

SoC R&D Trend for Future Digital Life
Ki Won LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C  No. 8  pp. 1705-1710
Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category: INVITED
Keyword: 
system-on-chipdigital convergence
  Summary |  Full Text:PDF (490.4KB)

Coupling-Driven Data Bus Encoding for SoC Video Architectures
Luca FANUCCI  Riccardo LOCATELLI  Andrea MINGHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12  pp. 3083-3090
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
bus encodingdeep sub-micronlow powersystem-on-chipvideo codingvery large scale integration architectures
  Summary |  Full Text:PDF (898.2KB)

A Single Cycle 16-Bit Microcontroller and DSP Core for Systems on Chips Solutions
Klaus D. MAIER 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2  pp. 339-346
Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Product Designs
Keyword: 
embedded microcontroller and DSPsystem-on-chip
  Summary |  Full Text:PDF (557.1KB)

Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products
Kunio UCHIYAMA  Fumio ARAKAWA  Yasuhiko SAITO  Koki NOGUCHI  Atsushi HASEGAWA  Shinichi YOSHIOKA  Naohiko IRIE  Takeshi KITAHARA  Mark DEBBAGE  Andy STURGES 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2  pp. 139-149
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
embedded processorRISCSIMDsystem-on-chipmultimedia
  Summary |  Full Text:PDF (1.6MB)