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Keyword : synchronous DRAM
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A Low Voltage High Speed Self-Timed CMOS Logic for the Multi-Gigabit Synchronous DRAM Application
Hoi-Jun YOO
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1997/08/20
Vol. E80-C
No. 8
pp. 1126-1128
Type of Manuscript: LETTER
Category: Integrated Electronics
Keyword:
low voltage,
self-timed CMOS logic,
synchronous DRAM,
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Full Text:PDF
(202.1KB)
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High Speed DRAMs with Innovative Architectures
Shigeo OHSHIMA
Tohru FURUYAMA
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/20
Vol. E77-C
No. 8
pp. 1303-1315
Type of Manuscript: INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: DRAM
Keyword:
DRAM,
memory bottleneck,
data bandwidth,
latency,
synchronous DRAM,
pipeline architecture,
data prefetching,
cache DRAM,
fast copyback,
Rambus interface,
Rambus DRAM,
protocol packet,
PLL,
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