Keyword : switching activity


Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation
Xin MAN Takashi HORIYAMA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8 ; pp. 1347-1358
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
actual power reductionautomatic multi-stage clock gating optimizationILP formulationswitching activityBDDMIP optimizer
 Summary | Full Text:PDF(2.8MB)

Low Power Bus Binding Exploiting Optimal Substructure
Ji-Hyung KIM Jun-Dong CHO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/01/01
Vol. E94-A  No. 1 ; pp. 332-341
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
low powerbus bindingswitching activitytable decompositionoptimal substructure
 Summary | Full Text:PDF(881.2KB)

Operation Mode Based High-Level Switching Activity Analysis for Power Estimation of Digital Circuits
Hyunchul SHIN Changhee LEE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2007/07/01
Vol. E90-B  No. 7 ; pp. 1826-1834
Type of Manuscript:  PAPER
Category: Energy in Electronics Communications
Keyword: 
low-power designcontrol signalpower estimationswitching activity
 Summary | Full Text:PDF(1.1MB)

High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks
Shinichi NODA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4 ; pp. 827-834
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
high-level synthesispower estimationgated clockswitching activitysequential circuit
 Summary | Full Text:PDF(500.8KB)

Power Estimation and Reduction of CMOS Circuits Considering Gate Delay
Hiroaki UEDA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/01/25
Vol. E82-D  No. 1 ; pp. 301-308
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
CMOS circuitlow power designgate delaytransition probabilityswitching activity
 Summary | Full Text:PDF(202.7KB)