Keyword : supercomputer


Set-to-Set Disjoint Paths Routing in Torus-Connected Cycles
Antoine BOSSARD Keiichi KANEKO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/11/01
Vol. E99-D  No. 11 ; pp. 2821-2823
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
torusmany-to-manyparallel systemfault-tolerancedependablesupercomputer
 Summary | Full Text:PDF(99.7KB)

Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits
Naofumi TAKAGI Kazuaki MURAKAMI Akira FUJIMAKI Nobuyuki YOSHIKAWA Koji INOUE Hiroaki HONDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/03/01
Vol. E91-C  No. 3 ; pp. 350-355
Type of Manuscript:  INVITED PAPER (Special Section on Recent Progress in Superconductive Digital Electronics)
Category: 
Keyword: 
superconductorrapid single-flux-quantum circuitreconfigurable data-pathhigh-performance computingsupercomputer
 Summary | Full Text:PDF(297.2KB)

The Development of the Earth Simulator
Shinichi HABATA Mitsuo YOKOKAWA Shigemune KITAWAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10 ; pp. 1947-1954
Type of Manuscript:  INVITED PAPER (Special Issue on Development of Advanced Computer Systems)
Category: 
Keyword: 
supercomputerHPC (high performance computing)parallel processingshared memoryvector processorcrossbar network
 Summary | Full Text:PDF(2.6MB)

Interprocessor Memory Access Arbitrating Scheme for TCMP Type Vector Supercomputer
Tadayuki SAKAKIBARA Katsuyoshi KITAI Tadaaki ISOBE Shigeko YAZAWA Teruo TANAKA Yoshiko TAMAKI Yasuhiro INAGAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/09/25
Vol. E80-D  No. 9 ; pp. 925-932
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Computer Architecture
Keyword: 
supercomputervector processorTCMParbitrateinterprocessor memory access conflict
 Summary | Full Text:PDF(868.2KB)

Scalable Parallel Memory Architecture with a Skew Scheme
Tadayuki SAKAKIBARA Katsuyoshi KITAI Tadaaki ISOBE Shigeko YAZAWA Teruo TANAKA Yasuhiro INAGAMI Yoshiko TAMAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/09/25
Vol. E80-D  No. 9 ; pp. 933-941
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Computer Architecture
Keyword: 
supercomputervector processorinterleaved parallel memoryskew schemememory access conflictpermanent-concentrationtransient-concentration
 Summary | Full Text:PDF(749.8KB)