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Keyword : standard cell
Study of Pattern Area Reduction for Standard Cell with SGT and Planar Transistor
Takahiro KODAMA
Shigeyoshi WATANABE
Publication:
C - Abstracts of IEICE TRANSACTIONS on Electronics (Japanese Edition)
Publication Date:
2011/06/01
Vol.
J94-C
No.
6
pp.
166-170
Type of Manuscript:
LETTER
Category:
Keyword:
SGT
,
system LSI
,
design rule
,
pattern area
,
standard cell
,
Summary
|
Full Text(in Japanese):PDF
(1MB)
