Keyword : source-coupled pair

A New Linear Transconductor Combining a Source Coupled Pair with a Transconductor Using Bias-Offset Technique
Isamu YAMAGUCHI  Fujihiko MATSUMOTO  Makoto IZUMA  Yasuaki NOGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2  pp. 369-376
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
MOS transistor,  linear transconductor,  bias-offset technique,  source-coupled pair,  mobility degradation, 
  Summary |  Full Text:PDF (1006.2KB)
An Equivalent MOSFET Cell Using Adaptively Biased Source-Coupled Pair
Hiroki SATO  Akira HYOGO  Keitaro SEKINE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/02/01
Vol. E86-A  No. 2  pp. 357-363
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
MOS analog circuit,  threshold voltage,  source-coupled pair,  adaptively bias technique, 
  Summary |  Full Text:PDF (842.6KB)
Design and Implementation of a Low-Power Multiple-Valued Current-Mode Integrated Circuit with Current-Source Control
Takahiro HANYU  Satoshi KAZAMA  Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/20
Vol. E80-C  No. 7  pp. 941-947
Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multiple-Valued Architectures
Keyword: 
54-bit multiplier,  signed-digit arithmetic,  differential logic circuit,  threshold detector,  source-coupled pair,  multi-phase clocking, 
  Summary |  Full Text:PDF (600.8KB)