Keyword : soft error rate (SER)


Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
Shusuke YOSHIMOTO Shunsuke OKUMURA Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/07/01
Vol. E96-A  No. 7 ; pp. 1579-1585
Type of Manuscript:  PAPER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
SRAMsoft error rate (SER)multiple cell upset (MCU)neutron particletwin welltriple well
 Summary | Full Text:PDF(2.6MB)

Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process
Shusuke YOSHIMOTO Takuro AMASHITA Shunsuke OKUMURA Koji NII Masahiko YOSHIMOTO Hiroshi KAWAGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8 ; pp. 1359-1365
Type of Manuscript:  PAPER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
SRAMsingle-event upset (SEU)bit error rate (BER)soft error rate (SER)neutron particlealpha particle
 Summary | Full Text:PDF(4MB)