Keyword : sequential circuit


A Single Input Change Test Pattern Generator for Sequential Circuits
Feng LIANG ShaoChong LEI ZhiBiao SHAO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/08/01
Vol. E91-C  No. 8 ; pp. 1365-1370
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
built-in self-test (BIST)single input change (SIC) sequenceseedsequential circuit
 Summary | Full Text:PDF(341.7KB)

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability
Masato NAKAZATO Satoshi OHTAKE Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1 ; pp. 296-305
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
sequential circuittest generationsynthesis for testabilityfinite state machinetest knowledge
 Summary | Full Text:PDF(641.6KB)

On Finding Don't Cares in Test Sequences for Sequential Circuits
Yoshinobu HIGAMI Seiji KAJIHARA Irith POMERANZ Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/11/01
Vol. E89-D  No. 11 ; pp. 2748-2755
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test generationdon't care valuesequential circuitstuck-at fault
 Summary | Full Text:PDF(195KB)

Timing Optimization Methodology Based on Replacing Flip-Flops by Latches
Ko YOSHIKAWA Keisuke KANAMARU Yasuhiko HAGIHARA Shigeto INUI Yuichi NAKAMURA Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3151-3158
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesissequential circuittiming optimizationlevel-sensitive latchformal verification
 Summary | Full Text:PDF(402.1KB)

Generation of Test Sequences with Low Power Dissipation for Sequential Circuits
Yoshinobu HIGAMI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 530-536
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Test Generation and Compaction
Keyword: 
LSI testingsequential circuittest generationlow power dissipationstuck-at fault
 Summary | Full Text:PDF(176KB)

Multi-Cycle Path Detection for Sequential Circuits and Its Application to Real Designs
Hiroyuki HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3176-3183
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
multi-cycle pathfalse pathsequential circuitimplicationATPGmultiple clock
 Summary | Full Text:PDF(414.4KB)

Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation
Hiroshi TAKAHASHI Marong PHADOONGSIDHI Yoshinobu HIGAMI Kewal K. SALUJA Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1515-1525
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
diagnosiscrosstalk faultfault simulationsequential circuit
 Summary | Full Text:PDF(870.8KB)

Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States
Hiroyuki YOTSUYANAGI Masaki HASHIZUME Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1605-1608
Type of Manuscript:  Special Section LETTER (Special Issue on Test and Verification of VLSI)
Category: 
Keyword: 
synthesis for testabilityredundancy removalsequential circuitundetectable faultsunreachable states
 Summary | Full Text:PDF(220.4KB)

High-Level Area/Delay/Power Estimation for Low Power System VLSIs with Gated Clocks
Shinichi NODA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4 ; pp. 827-834
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
high-level synthesispower estimationgated clockswitching activitysequential circuit
 Summary | Full Text:PDF(500.8KB)

Test Generation for Sequential Circuits under IDDQ Testing
Toshiyuki MAEDA Yoshinobu HIGAMI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 689-696
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: IDDQ Testing
Keyword: 
sequential circuittest generationIDDQ testingbridging fault
 Summary | Full Text:PDF(707.5KB)

A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits
Noriyoshi ITAZAKI Yasutaka IDOMOTO Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1 ; pp. 38-43
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Testing/Checking
Keyword: 
crosstalk faultfault simulationsequential circuittest
 Summary | Full Text:PDF(526.4KB)

Efficient Guided-Probe Fault Location Method for Sequential Circuits
Xiaoging WEN Kozo KINOSHITA Hideo TAMAMOTO Hiroshi YOKOYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/02/25
Vol. E78-D  No. 2 ; pp. 122-129
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
guided-probe fault locationselection of lines to probesequential circuitVLSI diagnosis
 Summary | Full Text:PDF(713KB)

A Reduced Scan Shift Method for Sequential Circuit Testing
Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2010-2016
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
sequential circuittest generationdesign for testabilityscan circuitreduced scan shift
 Summary | Full Text:PDF(625.9KB)

Test Sequence Generation for Sequential Circuits with Distinguishing Sequences
Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1730-1737
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
distinguishing sequencestuck-at faultsequential circuittest sequence generationdesign rechnique
 Summary | Full Text:PDF(696.2KB)

Synthesis of Testable Sequential Circuits with Reduced Checking Sequences
Satoshi SHIBATANI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 739-746
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
sequential circuitdesign for testabilityautomated logic synthesischecking sequencestate assignment
 Summary | Full Text:PDF(702.7KB)

A Testable Design of Sequential Circuits under Highly Observable Condition
WEN Xiaoqing Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/05/25
Vol. E75-D  No. 3 ; pp. 334-341
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
design for testabilityhighly observable testingfault diagnosissequential circuitcircuit modification
 Summary | Full Text:PDF(660.1KB)