IEICE SEARCH SYSTEM

Keyword : self-reconfigurable system

A System for Efficiently Self-Reconstructing 1(1/2)-Track Switch Torus Arrays Tadayoshi HORITA Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/12/01 Vol. E84-D No. 12 pp. 1801-1809 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: reconfiguration, 1(1/2)-track switch torus array, fault tolerance, wafer scale integration, self-reconfigurable system,
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An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults Tadayoshi HORITA Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/08/20 Vol. E83-D No. 8 pp. 1701-1705 Type of Manuscript: LETTER Category: Fault Tolerance Keyword: fault tolerant processor arrays, 1 1/2 track-switch model, self-reconfigurable system, run-time fault tolerance, wafer scale integration,
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A Built-In Self-Reconstruction Approach for Partitioned Mesh-Arrays Using Neural Algorithm Tadayoshi HORITA Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/08/20 Vol. E79-D No. 8 pp. 1160-1167 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Fault Diagnosis/Tolerance Keyword: mesh-array, fault tolerance, self-reconfigurable system, wafer scale integration, neural algorithm,
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