IEICE SEARCH SYSTEM

Keyword : router

A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method Hyuk-Jun LEE Seung-Chul KIM Eui-Young CHUNG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/04/01 Vol. E96-D No. 4 pp. 963-966 Type of Manuscript: LETTER Category: Computer System Keyword: router, packet memory, low power, TCP,
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Router Power Reduction through Dynamic Performance Control Based on Traffic Predictions Hiroyuki ITO Hiroshi HASEGAWA Ken-ichi SATO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2012/10/01 Vol. E95-B No. 10 pp. 3130-3138 Type of Manuscript: PAPER Category: Energy in Electronics Communications Keyword: router, performance control, energy efficiency,
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SOBR: A High-Performance Shared Output Buffered Router for Networks-on-Chip Yancang CHEN Lunguo XIE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/07/01 Vol. E95-D No. 7 pp. 2002-2005 Type of Manuscript: LETTER Category: Computer System Keyword: networks-on-chip, router, virtual channel, switching,
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Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks Po-Tsang HUANG Wei HWANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/11/01 Vol. E94-A No. 11 pp. 2412-2424 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: two-level FIFO buffer, centralized shared buffer, router, on-chip interconnection network,
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Fast Packet Classification Using Multi-Dimensional Encoding Chi Jia HUANG Chien CHEN
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2009/06/01 Vol. E92-B No. 6 pp. 2044-2053 Type of Manuscript: PAPER Category: Internet Keyword: router, packet classification, multi-dimensional encoding, bitmap intersection, network processor,
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A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/04/01 Vol. E92-D No. 4 pp. 575-583 Type of Manuscript: PAPER Category: VLSI Systems Keyword: network-on-chip, FPGA, customize, router,
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A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs Daihan WANG Hiroki MATSUTANI Michihiro KOIBUCHI Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 pp. 1914-1922 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable System and Applications Keyword: Networks-on-Chip, FPGA, router, port combination,
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Formalization and Analysis of Routing Loops by Inconsistencies in IP Forwarding Tables Kazuya SUZUKI Masahiro JIBIKI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2007/10/01 Vol. E90-B No. 10 pp. 2755-2763 Type of Manuscript: Special Section PAPER (Special Section on New Challenge for Internet Technology and its Architecture) Category: Keyword: high availability, routing protocol, the Internet, router,
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Low-Power Network-Packet-Processing Architecture Using Process-Learning Cache for High-End Backbone Router Michitaka OKUNO Shin-ichi ISHIDA Hiroaki NISHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 536-543 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Digital Keyword: router, Ethernet, packet-processing engine, network processor, cache-based packet-processing engine,
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A High-Speed Packet Classification Using TCAM Masanori UGA Masaaki OMOTANI Kohei SHIOMOTO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2002/09/01 Vol. E85-B No. 9 pp. 1766-1773 Type of Manuscript: PAPER Category: Internet Keyword: packet classification, TCAM, IPv6, router,
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Overview of DiffServ Technology: Its Mechanism and Implementation Takeshi AIMOTO Shigeru MIYAKE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2000/05/20 Vol. E83-D No. 5 pp. 957-964 Type of Manuscript: INVITED PAPER (Special Issue on Next Generation Internet Technologies and Their Applications) Category: Keyword: Internet, router, QoS, DiffServ, policy management,
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Scalable Internet Backbone Using Multi-Gigabit ATM-Based Connectionless Switching Shigehiko USHIJIMA Hiroyuki ICHIKAWA Katsunori NORITAKE Naoya WATANABE
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1998/02/20 Vol. E81-B No. 2 pp. 324-332 Type of Manuscript: Special Section PAPER (Special Issue on ATM Switching Systems for future B-ISDN) Category: ATM switch interworking Keyword: connectionless, Internet, router, ATM, gigabit, IP,
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CORErouter-I: An Experimental Parallel IP Router Using a Cluster of Workstations Mitsuru MARUYAMA Naohisa TAKAHASHI Takeshi MIEI Tsuyoshi OGURA Tetsuo KAWANO Satoru YAGI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1997/10/20 Vol. E80-B No. 10 pp. 1407-1414 Type of Manuscript: Special Section PAPER (Special Issue on Network Interworking) Category: System architecture Keyword: internet, router, TCP/IP, parallel processing, workstation cluster, routing protocol,
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The RDT Router Chip: A Versatile Router for Supporting a Distributed Shared Memory Hiroaki NISHI Ken-ichiro ANJO Tomohiro KUDOH Hideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/09/20 Vol. E80-D No. 9 pp. 854-862 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Interconnection Networks Keyword: router, interconnection network, cache coherent distributed shared memory,
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Architecture of Cell Switch Router and Prototype System Implementation Shigeo MATSUZAWA Ken'ichi NAGAMI Akiyoshi MOGI Tatsuya JINMEI Hiroshi ESAKI Yasuhiro KATSUBE
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1997/08/20 Vol. E80-B No. 8 pp. 1227-1238 Type of Manuscript: PAPER Category: Communication Networks and Services Keyword: ATM, CSR, cut-thru, hop-by-hop, IP, router, prototype,
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Proposal and Performance Evaluation of a High-Speed Internetworking Device Akira WATANABE Yuuji KOUI Shoichiro SENO Tetsuo IDEGUCHI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1996/05/20 Vol. E79-B No. 5 pp. 639-646 Type of Manuscript: Special Section PAPER (Special Issue on High Speed Local Area Network) Category: Keyword: router, performance, architecture, internetworking, evaluation,
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A Hierarchical Global Router for Mscro-Block-Embedded Sea-of-Gates Mototaka KURIBAYASHI Masaaki YAMADA Takashi MITSUHASHI Nobuyuki GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/20 Vol. E76-A No. 10 pp. 1694-1704 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: VLSI, CAD, router, hierarchical decomposition,
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A Distributed Routing System for Multilayer SOG Takashi SHIMAMOTO Isao SHIRAKAWA Hidetaka HANE Nobuyasu YUI Nobuyuki NISHIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/03/20 Vol. E76-A No. 3 pp. 370-376 Type of Manuscript: Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems) Category: Keyword: router, distribution, SOG, rip-up and reroute, variable-cost maze,
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