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Keyword : redundancy

Robust Cyclic ADC Architecture Based on β-Expansion Rie SUZUKI Tsubasa MARUYAMA Hao SAN Kazuyuki AIHARA Masao HOTTA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 553-559 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: robust ADC, β-expansion, redundancy, cyclic ADC, radix-value estimation algorithm,
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Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs Chizu MATSUMOTO Yuichi HAMAMURA Michinobu NAKAO Kaname YAMASAKI Yoshikazu SAITO Shun'ichi KANEKO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/01/01 Vol. E96-C No. 1 pp. 108-114 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: random access memory, system-on-chip, redundancy, fuse,
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SAR ADC Algorithm with Redundancy and Digital Error Correction Tomohiko OGAWA Haruo KOBAYASHI Yosuke TAKAHASHI Nobukazu TAKAI Masao HOTTA Hao SAN Tatsuji MATSUURA Akira ABE Katsuyoshi YAGI Toshihiko MORI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/02/01 Vol. E93-A No. 2 pp. 415-423 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: SAR ADC, digital error correction, non-binary, redundancy,
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Distributed Stable Flooding Using Delay Function Based on Redundancy Wonjong NOH
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2009/12/01 Vol. E92-B No. 12 pp. 3923-3926 Type of Manuscript: LETTER Category: Network Keyword: delayed flooding, redundancy, sensor/ad-hoc network,
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A Novel Approach to Overlay Multicasting Schemes for Multi-Hop Ad-Hoc Networks Namhi KANG Jejun OH Younghan KIM
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2008/06/01 Vol. E91-B No. 6 pp. 1862-1873 Type of Manuscript: PAPER Category: Network Keyword: ad-hoc networks, overlay multicasting, routing, redundancy, performance evaluation,
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An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches Tadayoshi HORITA Yuuji KATOU Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/02/01 Vol. E91-A No. 2 pp. 623-632 Type of Manuscript: PAPER Category: Reliability, Maintainability and Safety Analysis Keyword: 3D mesh-connected processor arrays, 1.5-track switches, reconfiguration, fault tolerance, redundancy,
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Constitutive Synthesis of Physiological Networks Seiichiro NAKABAYASHI Nobuko TANIMURA Toshikazu YAMASHITA Shinichiro KOKUBUN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/01/01 Vol. E90-C No. 1 pp. 116-119 Type of Manuscript: Special Section PAPER (Special Section on Microoptomechatronics) Category: INVITED Keyword: nonlinear oscillator, complex network, physiological functions, robustness, redundancy,
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Analysis of Zero-Redundancy Estimator with a Finite Window for Markovian Source Mohammad M. RASHID Tsutomu KAWABATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/10/01 Vol. E88-A No. 10 pp. 2819-2825 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Information Theory Keyword: universal source coding, redundancy, zero-redundancy estimator, Markov source,
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Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories Kiyohiro FURUTANI Takeshi HAMAMOTO Takeo MIKI Masaya NAKANO Takashi KONO Shigeru KIKUDA Yasuhiro KONISHI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/02/01 Vol. E88-C No. 2 pp. 255-263 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: DRAM, redundancy, high speed, high density,
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A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks Yu-Liang WU Wangning LONG Hongbing FAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/06/20 Vol. E83-A No. 6 pp. 1131-1137 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99)) Category: Keyword: rewiring, logic synthesis, circuit minimization, redundancy,
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Real-Time Restoration of Nonstationary Biomedical Signals under Additive Noises Junichi HORI Yoshiaki SAITOH Tohru KIRYU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/10/20 Vol. E82-D No. 10 pp. 1409-1416 Type of Manuscript: PAPER Category: Medical Electronics and Medical Information Keyword: restoration, band-limitation, real-time, additive noise, redundancy,
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A Board Level Parallel Test Circuit and a Short Circuit Failure Repair Circuit for High-Density, Low-Power DRAMs Kiyohiro FURUTANI Tsukasa OOISHI Mikio ASAKURA Hideto HIDAKA Hideyuki OZAKI Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/20 Vol. E80-C No. 4 pp. 582-589 Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs) Category: Keyword: DRAM, test, redundancy,
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Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOSSRAM Kenichi OHHATA Takeshi KUSUNOKI Hiroaki NAMBU Kazuo KANETANI Toru MASUDA Masayuki OHAYASHI Satomi HAMAMOTO Kunihiko YAMAGUCHI Youji IDEI Noriyuki HOMMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/03/20 Vol. E79-C No. 3 pp. 415-423 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: redundancy, ECL-CMOS SRAM, SRAM with logic gate, BiCMOS,
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A Method to Reduce Redundant Hidden Nodes Iwao SEKITA Takio KURITA David K. Y. CHIU Hideki ASOH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1994/04/20 Vol. E77-D No. 4 pp. 443-449 Type of Manuscript: Special Section PAPER (Special Issue on Neurocomputing) Category: Network Synthesis Keyword: neural network, redundancy, linearly dependent, regression, PCA,
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Estimation of Yield Suppression for 1.5 V-1 Gbit DRAMs Caused by Threshold Voltage Variation of MOSFET due to Microscopic Fluctuation in Dopant Distributions Shigeyoshi WATANABE Takaaki MINAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/02/20 Vol. E77-C No. 2 pp. 273-279 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: 1 Gbit DRAM, 1.5 V, yield, threshold voltage variation, redundancy,
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Statistical Memory Yield Analysis and Redundancy Design Considering Fabrication Line Improvement Ken-ichi IMAMIYA Jun-ichi MIYAMOTO Nobuaki OHTSUKA Naoto TOMITA Yumiko IYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/20 Vol. E76-C No. 11 pp. 1626-1631 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Non-volatile Memory Keyword: redundancy, memory, yield, EPROM,
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A Bitline Control Circuit Scheme and Redundancy Technique for High-Density Dynamic Content Addressable Memories Tadato YAMAGATA Masaaki MIHARA Takeshi HAMAMOTO Yasumitsu MURAI Toshifumi KOBAYASHI Michihiro YAMADA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/20 Vol. E76-C No. 11 pp. 1657-1664 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: content addressable memory, associative memory, dynamic memory, redundancy,
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Eliminating Redundant Components While Building Solid Models by Surface Points Evaluation Chun YANG Shan Jun ZHANG Toshio KAWASHIMA Yoshinao AOKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/11/20 Vol. E75-A No. 11 pp. 1561-1569 Type of Manuscript: PAPER Category: Computer Aided Design (CAD) Keyword: CSG, B-reps, redundancy, dispersed surface points set, geometry shape block, null block, sample boundary segment,
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