Keyword : reconfiguration


The Reliability Analysis of the 1-out-of-2 System in Which Two Modules Do Mutual Cooperation in Recovery Mode
Aromhack SAYSANASONGKHAM Satoshi FUKUMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/09/01
Vol. E99-A  No. 9 ; pp. 1730-1734
Type of Manuscript:  LETTER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
1-out-of-2 systemreliability analysisMarkov chainunreliabilityparallel redundant systemhardware restorationdata reconstructionmutual cooperationFPGAreconfiguration
 Summary | Full Text:PDF(260.3KB)

Pre-Adjustment Rerouting for Wavelength Defragmentation in Optical Transparent WDM Networks
Akihiro KADOHATA Atsushi WATANABE Akira HIRANO Hiroshi HASEGAWA Ken-ichi SATO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2015/10/01
Vol. E98-B  No. 10 ; pp. 2014-2021
Type of Manuscript:  PAPER
Category: Fiber-Optic Transmission for Communications
Keyword: 
optical transparent wdm networksreconfigurationdefragmentation
 Summary | Full Text:PDF(1.7MB)

The List Coloring Reconfiguration Problem for Bounded Pathwidth Graphs
Tatsuhiko HATANAKA Takehiro ITO Xiao ZHOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/06/01
Vol. E98-A  No. 6 ; pp. 1168-1178
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graph algorithmlist coloringpathwidthPSPACE-completereachability on solution spacereconfiguration
 Summary | Full Text:PDF(957.4KB)

RONoC: A Reconfigurable Architecture for Application-Specific Optical Network-on-Chip
Huaxi GU Zheng CHEN Yintang YANG Hui DING 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/01/01
Vol. E97-D  No. 1 ; pp. 142-145
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
reconfigurationoptical Network-on-Chipapplication-specificoptical router
 Summary | Full Text:PDF(791.7KB)

Finite Virtual State Machines
Raouf SENHADJI-NAVARRO Ignacio GARCIA-VARGAS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/10/01
Vol. E95-D  No. 10 ; pp. 2544-2547
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
finite state machinereconfigurationRAMFPGA
 Summary | Full Text:PDF(330.4KB)

An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
Tadayoshi HORITA Yuuji KATOU Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2 ; pp. 623-632
Type of Manuscript:  PAPER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
3D mesh-connected processor arrays1.5-track switchesreconfigurationfault toleranceredundancy
 Summary | Full Text:PDF(757.9KB)

Introduction to IEEE P1900.4 Activities
Soodesh BULJORE Markus MUCK Patricia MARTIGNE Paul HOUZE Hiroshi HARADA Kentaro ISHIZU Oliver HOLLAND Andrej MIHAILOVIC Kostas A. TSAGKARIS Oriol SALLENT Gary CLEMO Mahesh SOORIYABANDARA Vladimir IVANOV Klaus NOLTE Makis STAMETALOS 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/01/01
Vol. E91-B  No. 1 ; pp. 2-9
Type of Manuscript:  INVITED PAPER (Special Section on Cognitive Radio and Spectrum Sharing Technology)
Category: 
Keyword: 
IEEE standardizationcognitive radionetwork architecturereconfigurationheterogeneous radio access networksdistributed radio resource management
 Summary | Full Text:PDF(1008.3KB)

Query-Transaction Acceleration Using a DRP Enabling High-Speed Stateful Packet-by-Packet Self-Reconfiguration
Takashi ISOBE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12 ; pp. 1905-1913
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable System and Applications
Keyword: 
query-transactionstatefulpacket-by-packetreconfigurationdynamic reconfigurable processor
 Summary | Full Text:PDF(4MB)

Multiple Sequence Alignment Based on Dynamic Programming Using FPGA
Shingo MASUNO Tsutomu MARUYAMA Yoshiki YAMAGUCHI Akihiko KONAGAYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12 ; pp. 1939-1946
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable System and Applications
Keyword: 
multiple sequence alignmentdynamic programmingFPGAreconfiguration
 Summary | Full Text:PDF(436.1KB)

Reconfiguration Heuristics for Logical Topologies in Wide-Area WDM Networks
Hironao TAKAGI Yongbing ZHANG Hideaki TAKAGI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/07/01
Vol. E89-B  No. 7 ; pp. 1994-2001
Type of Manuscript:  PAPER
Category: Fiber-Optic Transmission for Communications
Keyword: 
lightpathlogical topologyreconfigurationwavelength-division multiplexingoptical networks
 Summary | Full Text:PDF(351.3KB)

On Reconfiguring Radial Trees
Yoshiyuki KUSAKARI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/05/01
Vol. E89-A  No. 5 ; pp. 1207-1214
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
linkagereconfigurationstraighteningflatteningmonotone treeradial tree
 Summary | Full Text:PDF(233.2KB)

Self-Reconfiguring of -Track-Switch Mesh Arrays with Spares on One Row and One Column by Simple Built-in Circuit
Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/10/01
Vol. E87-D  No. 10 ; pp. 2318-2328
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
mesh arrayfault-tolerancereconfigurationself-repairbuilt-in circuit
 Summary | Full Text:PDF(765.4KB)

Reconfiguration Classes and an Optimal Reconfiguration Method within a Reconfiguration Class
Noritaka SHIGEI Hiromi MIYAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/12/01
Vol. E85-D  No. 12 ; pp. 1909-1917
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
processor arrayreconfigurationfault tolerantreconfiguration classesinclusion relation
 Summary | Full Text:PDF(1.2MB)

A System for Efficiently Self-Reconstructing 1(1/2)-Track Switch Torus Arrays
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/12/01
Vol. E84-D  No. 12 ; pp. 1801-1809
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
reconfiguration1(1/2)-track switch torus arrayfault tolerancewafer scale integrationself-reconfigurable system
 Summary | Full Text:PDF(787.5KB)

On the Search for Effective Spare Arrangement of Reconfigurable Processor Arrays Using Genetic Algorithm
Noritaka SHIGEI Hiromi MIYAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/09/25
Vol. E81-A  No. 9 ; pp. 1898-1901
Type of Manuscript:  Special Section LETTER (Special Section on Nonlinear Theory and Its Applications)
Category: Genetic Algorithm
Keyword: 
genetic algorithmprocessor arrayreconfigurationspare arrangement
 Summary | Full Text:PDF(331.2KB)

On Efficient Spare Arrangements and an Algorithm with Relocating Spares for Reconfiguring Processor Arrays
Noritaka SHIGEI Hiromi MIYAJIMA Sadayuki MURASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Vol. E80-A  No. 6 ; pp. 988-995
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
Category: 
Keyword: 
processor arrayreconfigurationfabrication yieldspare processorWSI
 Summary | Full Text:PDF(659.1KB)

On Methods for Reconfiguring Processor Arrays
Noritaka SHIGEI Hiromi MIYAJIMA Takayuki ISHIZAKA Sadayuki MURASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8 ; pp. 1139-1146
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Interconnection Networks
Keyword: 
processor arrayreconfigurationfabrication yieldspare processorWSI
 Summary | Full Text:PDF(715.3KB)

Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs
Yoshichika FUJIOKA Michitaka KAMEYAMA Nobuhiro TOMABECHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7 ; pp. 1123-1130
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
delay timemulti-operand multiply-additionreconfigurationdigital controlFPGA
 Summary | Full Text:PDF(673.7KB)

Analysis of Fault Tolerance of Reconfigurable Arrays Using Spare Processors
Kazuo SUGIHARA Tohru KIKUNO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/05/25
Vol. E75-D  No. 3 ; pp. 315-324
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
fault-tolerant computingoptimum fault toleranceprocessor arraysreconfigurable arraysreconfiguration
 Summary | Full Text:PDF(728.1KB)