IEICE SEARCH SYSTEM

Keyword : reconfigurable architecture

A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms Shuangqu HUANG Xiaoyang ZENG Yun CHEN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 403-412 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Application Keyword: iterative decoding, LDPC codes, reconfigurable architecture, TDMP, TPMP,
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Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband Platform Shuang ZHAO Wenqing LU Xiaofang ZHOU Dian ZHOU Gerald E. SOBELMAN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/04/01 Vol. E93-D No. 4 pp. 811-821 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: MIMO-OFDM, reconfigurable architecture, FFT, STBD, algorithm implementation,
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Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application Yiqing HUANG Qin LIU Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/11/01 Vol. E92-A No. 11 pp. 2819-2829 Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Video Coding Keyword: reconfigurable architecture, H.264/AVC, SAD tree, VLSI, HDTV,
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Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors Ittetsu TANIGUCHI Praveen RAGHAVAN Murali JAYAPALA Francky CATTHOOR Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 pp. 1161-1173 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: address generation unit (AGU), reconfigurable architecture, ASIP design, architecture exploration,
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Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures Jinhwan KIM Jeonghun CHO Tag Gon KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 pp. 1977-1985 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable Device and Design Tools Keyword: temporal partitioning, reconfigurable architecture, partial reconfiguration, dynamic reconfiguration, run-time reconfiguration and high-level synthesis,
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Reconfigurable Inner Product Hardware Architecture for Increased Hardware Utilization in SDR Systems Kwangsup SO Jinsang KIM Won-Kyung CHO Young-Soo KIM Doug Young SUH
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2006/12/01 Vol. E89-B No. 12 pp. 3242-3249 Type of Manuscript: Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications) Category: Keyword: inner product, pipelined multiplier, reconfigurable architecture, software defined radio,
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A Design Algorithm for Sequential Circuits Using LUT Rings Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3342-3350 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: reconfigurable architecture, LUT cascade, BDD_for_CF, functional decomposition,
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Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture Masanori HARIYAMA Weisheng CHONG Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1897-1902 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: reconfigurable architecture, FPGA, bit-serial architecture,
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An Innovative Architecture of CMAC Kao-Shing HWANG Yuan-Pao HSU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/01/01 Vol. E87-C No. 1 pp. 81-93 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: neural network, CMAC, CAM, reconfigurable architecture,
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A Low Cost Reconfigurable Architecture for a UMTS Receiver Ronny VELJANOVSKI Aleksandar STOJCEVSKI Jugdutt SINGH Aladin ZAYEGH Michael FAULKNER
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2003/12/01 Vol. E86-B No. 12 pp. 3441-3451 Type of Manuscript: Special Section PAPER (Special Issue on Software Defined Radio Technology and Its Applications) Category: Keyword: adjacent channel interference, pulse-shaping filter, pipeline ADC, reconfigurable architecture, UTRA-TDD,
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An Efficiently Self-Reconstructing Array System Using E-1-Track Switches Tadayoshi HORITA Itsuo TAKANAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/12/01 Vol. E86-D No. 12 pp. 2743-2752 Type of Manuscript: PAPER Category: Fault Tolerance Keyword: mesh-connected processor arrays, 1-track switches, E-1-track switches, fault-tolerance, reconfigurable architecture,
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A Flexible Architecture for Digital Signal Processing Wichai BOONKUMKLAO Yoshikazu MIYANAGA Kobchai DEJHAN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/10/01 Vol. E86-D No. 10 pp. 2179-2186 Type of Manuscript: PAPER Category: VLSI Systems Keyword: FRM, PCA, reconfigurable architecture, IP, VHDL,
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PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model--Design and Implementation of Its Prototype Processor Kazuya TANIGAWA Tetsuo HIRONAKA Akira KOJIMA Noriyoshi YOSHIDA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/05/01 Vol. E86-D No. 5 pp. 830-840 Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing) Category: Keyword: reconfigurable architecture, I-PARS execution model, general purpose, PARS architecture, design and implementation,
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RHINE: Reconfigurable Multiprocessor System for Video CODEC Yoshinori TAKEUCHI Zhao-Chen HUANG Masatomo SAEKI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/06/20 Vol. E76-A No. 6 pp. 947-956 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92)) Category: Methods and Circuits for Signal Processing Keyword: parallel processing, load balancing, video CODEC, parallel architecture, reconfigurable architecture,
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