Keyword : processor array


Reconfiguration Classes and an Optimal Reconfiguration Method within a Reconfiguration Class
Noritaka SHIGEI Hiromi MIYAJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/12/01
Vol. E85-D  No. 12 ; pp. 1909-1917
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
processor arrayreconfigurationfault tolerantreconfiguration classesinclusion relation
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On the Search for Effective Spare Arrangement of Reconfigurable Processor Arrays Using Genetic Algorithm
Noritaka SHIGEI Hiromi MIYAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/09/25
Vol. E81-A  No. 9 ; pp. 1898-1901
Type of Manuscript:  Special Section LETTER (Special Section on Nonlinear Theory and Its Applications)
Category: Genetic Algorithm
Keyword: 
genetic algorithmprocessor arrayreconfigurationspare arrangement
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On Efficient Spare Arrangements and an Algorithm with Relocating Spares for Reconfiguring Processor Arrays
Noritaka SHIGEI Hiromi MIYAJIMA Sadayuki MURASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Vol. E80-A  No. 6 ; pp. 988-995
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
Category: 
Keyword: 
processor arrayreconfigurationfabrication yieldspare processorWSI
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Memory Sharing Processor Array (MSPA) Architecture
Dongju LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12 ; pp. 2086-2096
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
processor arraydata-path synthesissystolic array
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Automatic Synthesis of a Serial Input Multiprocessor Array
Dongji LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12 ; pp. 2097-2105
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
processor arraydata-path synthesisserial interfacemultiplier
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On Methods for Reconfiguring Processor Arrays
Noritaka SHIGEI Hiromi MIYAJIMA Takayuki ISHIZAKA Sadayuki MURASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8 ; pp. 1139-1146
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Interconnection Networks
Keyword: 
processor arrayreconfigurationfabrication yieldspare processorWSI
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A Comparison between the Computational Power of PARBS and RMBM
Kensuke MIYASHITA Yoshihiro TSUJINO Nobuki TOKURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/05/25
Vol. E79-D  No. 5 ; pp. 570-578
Type of Manuscript:  PAPER
Category: Algorithm and Computational Complexity
Keyword: 
parallel computational modelprocessor arrayreconfigurable busPARBSRMBM
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Optimal Sorting Algorithms on Bus-Connected Processor Arrays
Koji NAKANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/11/25
Vol. E76-A  No. 11 ; pp. 2008-2015
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
sortingparallel algorithmprocessor arraybus
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The Trend of Functional Memory Development
Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1545-1554
Type of Manuscript:  INVITED PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
memoryfunctional memorycontent addressable memoryassociative memoryprocessor array
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