IEICE SEARCH SYSTEM

Keyword : processor architecture

Register Indirect Jump Target Forwarding Ryota SHIOYA Naruki KURATA Takashi TOYOSHIMA Masahiro GOSHIMA Shuichi SAKAI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/02/01 Vol. E96-D No. 2 pp. 278-288 Type of Manuscript: PAPER Category: Computer System Keyword: processor architecture, register indirect jump, object-oriented programming,
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Architecture and Implementation of a Reduced EPIC Processor Jun GAO Minxuan ZHANG Zuocheng XING Chaochao FENG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/01/01 Vol. E96-D No. 1 pp. 9-18 Type of Manuscript: PAPER Category: Computer System Keyword: ILP, EPIC, IA-64, processor architecture, hardware implementation,
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Low-Overhead Architecture for Security Tag Ryota SHIOYA Daewung KIM Kazuo HORIO Masahiro GOSHIMA Shuichi SAKAI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/01/01 Vol. E94-D No. 1 pp. 69-78 Type of Manuscript: PAPER Category: Computer System Keyword: processor architecture, tagged architecture, information security, information flow tracking,
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VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation Noriyuki MINEGISHI Junichi MIYAKOSHI Yuki KURODA Tadayoshi KATAGIRI Yuki FUKUYAMA Ryo YAMAMOTO Masayuki MIYAMA Kousuke IMAMURA Hideo HASHIMOTO Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 230-242 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: System LSIs and Microprocessors Keyword: optical flow, processor architecture, video segmentation,
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Reducing Memory System Energy by Software-Controlled On-Chip Memory Masaaki KONDO Hiroshi NAKAMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 580-588 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Architecture and Algorithms Keyword: processor architecture, cache, on-chip memory, way activation, memory traffic,
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Code Efficiency Evaluation for Embedded Processors Morgan Hirosuke MIKI Mamoru SAKAMOTO Shingo MIYAMOTO Yoshinori TAKEUCHI Toyohiko YOSHIDA Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 pp. 811-818 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: code efficiency, profiling, processor architecture,
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Reducing Cache Energy Dissipation by Using Dual Voltage Supply Vasily G. MOSHNYAGA Hiroshi TSUJI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2762-2768 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Optimization of Power and Timing Keyword: cache, processor architecture, low-power,
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Trends in High-Performance, Low-Power Processor Architectures Kazuaki MURAKAMI Hidetaka MAGOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 131-138 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: processor architecture, high performance design, low power design,
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ASIC Approaches for Vision-Based Vehicle Guidance Ichiro MASAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/12/20 Vol. E76-C No. 12 pp. 1735-1743 Type of Manuscript: INVITED PAPER (Special Issue on ASICs for Automotive Electronics) Category: Keyword: ASIC, stereo vision, intelligent vehicles, processor architecture,
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