Keyword : process variation


LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization
Yu HU Jing YE Zhiping SHI Xiaowei LI 
Publication:   
Publication Date: 2017/02/01
Vol. E100-D  No. 2 ; pp. 323-331
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
process variationtiming variationsamplepath selectionleast square
 Summary | Full Text:PDF(1.7MB)

A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model
Ahmed AWAD Atsushi TAKAHASHI Chikaaki KODAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2363-2374
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
pattern fidelityprocess variationmask manufacturabilitymask data volumecomputation time
 Summary | Full Text:PDF(1.7MB)

A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design
Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1278-1293
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
high-level synthesisprocess variationinterconnection delaydistributed-register architecturescenario
 Summary | Full Text:PDF(2.4MB)

Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs
Michitarou YABUUCHI Ryo KISHIDA Kazutoshi KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2367-2372
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
BTIprocess variationreliability
 Summary | Full Text:PDF(1.2MB)

Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis
Shiho HAGIWARA Takanori DATE Kazuya MASU Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4 ; pp. 280-288
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
design for manufacturingMonte Carlo methodimportance samplingSRAMprocess variationyieldnorm minimizationGaussian mixture modelsclusteringhypersphere sampling
 Summary | Full Text:PDF(1.1MB)

A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations
Susumu KOBAYASHI Fumihiro MINAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 1980-1985
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
clock skewinterconnectprocess variationsignal delay
 Summary | Full Text:PDF(1.3MB)

A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning
Shuta KIMURA Masanori HASHIMOTO Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2292-2300
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
post-silicon tuningbody bias clusteringprocess variationbody biasingstatistical static timing analysis
 Summary | Full Text:PDF(1.1MB)

A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits
Junya KAWASHIMA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2242-2250
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
subthreshold operationprocess variationminimum operation voltage estimationenergy minimizationyield maximization
 Summary | Full Text:PDF(837.1KB)

Layout-Aware Variability Characterization of CMOS Current Sources
Bo LIU Bo YANG Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 696-705
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
process variationcurrent mismatchlayout-dependent variationanalog DFM
 Summary | Full Text:PDF(1.9MB)

A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing
Yohei NAKATA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 523-533
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
network-on-chipprocess variationadaptive circuitsrouting algorithm
 Summary | Full Text:PDF(2.2MB)

Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit
Kei MATSUMOTO Tetsuya HIROSE Yuji OSAKI Nobutaka KUROKI Masahiro NUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6 ; pp. 1042-1048
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
SRAMthreshold voltage variationcompensation circuitprocess variationtemperature variationPVT variation
 Summary | Full Text:PDF(837.7KB)

Stochastic Non-homogeneous Arnoldi Method for Analysis of On-Chip Power Grid Networks under Process Variations
Zhihua GUI Fan YANG Xuan ZENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4 ; pp. 504-510
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
process variationpower gridnon-homogeneousARnoldi
 Summary | Full Text:PDF(555.8KB)

Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits
Pei-Wen LUO Jwu-E CHEN Chin-Long WEY 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/01/01
Vol. E94-A  No. 1 ; pp. 352-361
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
yield enhancementmismatchcommon centroidspatial correlationprocess variationplacement optimization
 Summary | Full Text:PDF(6.5MB)

Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization
Mahmoud MOMTAZPOUR Maziar GOUDARZI Esmaeil SANAEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2542-2550
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
process variationtask schedulingpower yieldMPSoC
 Summary | Full Text:PDF(589.4KB)

A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation
Takumi UEZONO Kazuya MASU Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 324-331
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
voltage measurementspatial voltage drop fluctuationprocess variationpower/signal integrity
 Summary | Full Text:PDF(665.2KB)

Testable Critical Path Selection Considering Process Variation
Xiang FU Huawei LI Xiaowei LI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1 ; pp. 59-67
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
testable critical path selectionprocess variation
 Summary | Full Text:PDF(503.7KB)

Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques
Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3079-3081
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
voltage-controlled oscillatorprocess variationprocess compensationbody biascurrent reference
 Summary | Full Text:PDF(314.6KB)

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
Takaaki OKUMURA Atsushi KUROKAWA Hiroo MASUDA Toshiki KANAMOTO Masanori HASHIMOTO Hiroshi TAKAFUJI Hidenari NAKASHIMA Nobuto ONO Tsuyoshi SAKATA Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 990-997
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
SSTAoutputtransition timegate delay modelprocess variation
 Summary | Full Text:PDF(2.6MB)

One-Shot Voltage-Measurement Circuit Utilizing Process Variation
Takumi UEZONO Takashi SATO Kazuya MASU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 1024-1030
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
voltage measurementprocess variationpower/signal integrity
 Summary | Full Text:PDF(525.2KB)

A Linear Fractional Transform (LFT) Based Model for Interconnect Uncertainty
Omar HAFIZ Alexander MITEV Janet Meiling WANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 1148-1160
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
uncertaintyprocess variationvariational model order reductionlinear fractional transform (LFT)balanced truncation realization (BTR)linear matrix inequality (LMI)
 Summary | Full Text:PDF(327.9KB)

A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop
Yoshiyuki KAWAKAMI Makoto TERAO Masahiro FUKUI Shuji TSUKIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3423-3430
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
power grid optimizationtiming violationcritical pathprocess variationIR drop
 Summary | Full Text:PDF(1MB)

Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays
Atsushi KUROKAWA Hiroo MASUDA Junko FUJII Toshinori INOSHITA Akira KASEBE Zhangcai HUANG Yasuaki INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 856-864
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
interconnectworst-case delaystatic timing analysisprocess variationcapacitance extraction
 Summary | Full Text:PDF(509.1KB)

Interconnect Modeling in Deep-Submicron Design
Won-Young JUNG Soo-Young OH Jeong-Taek KONG Keun-Ho LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/08/25
Vol. E83-C  No. 8 ; pp. 1311-1316
Type of Manuscript:  INVITED PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99))
Category: Circuit Applications
Keyword: 
statistical interconnect library generationinterconnect modelingMonte Carlo methodprocess variation
 Summary | Full Text:PDF(577.5KB)