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Keyword : power consumption
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Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture Ce LI
Yiping DONG
Takahiro WATANABE
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12
pp. 2519-2527
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design Keyword: FPGA,
low power,
power domain,
power consumption,
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Summary |
Full Text:PDF
(7.7MB)
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Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit Tadayoshi ENOMOTO
Nobuaki KOBAYASHI
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C
No. 4
pp. 409-416
Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: Keyword: clocks,
CMOS digital circuits,
power consumption,
SPICE,
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(1.2MB)
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Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs Yuichi NAKAMURA
Takeshi YOSHIMURA
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A
No. 12
pp. 3458-3463
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification Keyword: SoC,
power consumption,
power estimation,
toggle rate,
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(724.8KB)
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LP Based Cell Selection with Constraints of Timing, Area, and Power Consumption Yutaka TAMIYA
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/20
Vol. E78-A
No. 3
pp. 331-336
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD Keyword: gate sizing,
timing optimization,
power consumption,
linear programming,
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Full Text:PDF
(467.4KB)
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