Keyword : power analysis

Correlated Noise Reduction for Electromagnetic Analysis
Hongying LIU  Xin JIN  Yukiyasu TSUNOO  Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/01/01
Vol. E96-A  No. 1  pp. 185-195
Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Implementation
Keyword: 
electromagnetic analysis (EMA),  power analysis,  electromagnetic leakage,  correlated noise,  singular value decomposition, 
  Summary |  Full Text:PDF (2.9MB)
Performance Improvement of Power Analysis Attacks on AES with Encryption-Related Signals
You-Seok LEE  Young-Jun LEE  Dong-Guk HAN  Ho-Won KIM  Hyoung-Nam KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/06/01
Vol. E95-A  No. 6  pp. 1091-1094
Type of Manuscript: LETTER
Category: Cryptography and Information Security
Keyword: 
power analysis,  side-channel attack,  security, 
  Summary |  Full Text:PDF (206.5KB)
Modified Doubling Attack by Exploiting Chosen Ciphertext of Small Order
Sung-Ming YEN  Wei-Chih LIEN  Chien-Ning CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/10/01
Vol. E94-A  No. 10  pp. 1981-1990
Type of Manuscript: PAPER
Category: Cryptography and Information Security
Keyword: 
doubling attack,  elliptic curve cryptosystem,  power analysis,  RSA,  side-channel analysis,  smart cards, 
  Summary |  Full Text:PDF (338.2KB)
BS-CPA: Built-In Determined Sub-Key Correlation Power Analysis
Yuichi KOMANO  Hideo SHIMIZU  Shinichi KAWAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/09/01
Vol. E93-A  No. 9  pp. 1632-1638
Type of Manuscript: PAPER
Category: Cryptography and Information Security
Keyword: 
side channel attacks,  power analysis,  CPA,  Hamming weight and Hamming distance models,  DPA contest, 
  Summary |  Full Text:PDF (424.6KB)
Power Analysis and Estimation for SOC Design: Techniques and Tools
Yun CAO  Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/02/01
Vol. E87-A  No. 2  pp. 410-416
Type of Manuscript: REVIEW PAPER
Category: VLSI Design Technology and CAD
Keyword: 
low power,  SOC,  power analysis,  power estimation, 
  Summary |  Full Text:PDF (248.4KB)
Pre-Route Power Analysis Techniques for SoC
Takashi YAMADA  Takeshi SAKAMOTO  Shinji FURUICHI  Mamoru MUKUNO  Yoshifumi MATSUSHITA  Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/03/01
Vol. E86-A  No. 3  pp. 686-692
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoC,  power analysis,  gate-level,  custom wire load model, 
  Summary |  Full Text:PDF (765.4KB)
Power Analysis of a Programmable DSP for Architecture and Program Optimization
Hirotsugu KOJIMA  Douglas J. GORNY  Kenichi NITTA  Avadhani SHRIDHAR  Katsuro SASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/20
Vol. E79-C  No. 12  pp. 1686-1692
Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
low-power,  power analysis,  DSP,  power simulation, 
  Summary |  Full Text:PDF (667.6KB)