Keyword : pipeline


A Low-Latency Parallel Pipeline CORDIC
Hong-Thu NGUYEN Xuan-Thuan NGUYEN Cong-Kha PHAM 
Publication:   
Publication Date: 2017/04/01
Vol. E100-C  No. 4 ; pp. 391-398
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
CORDICpipelinelow-latency
 Summary | Full Text:PDF(1.3MB)

Hybrid MIC/CPU Parallel Implementation of MoM on MIC Cluster for Electromagnetic Problems
Yan CHEN Yu ZHANG Guanghui ZHANG Xunwang ZHAO ShaoHua WU Qing ZHANG XiaoPeng YANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/07/01
Vol. E99-C  No. 7 ; pp. 735-743
Type of Manuscript:  INVITED PAPER (Special Section on Recent Advances in Simulation Techniques and Their Applications for Electronics)
Category: 
Keyword: 
MIC accelerating MoMMPI and OpenMP parallel programming modemultiple nodesout-of-corepipeline
 Summary | Full Text:PDF(1.7MB)

A SoC Integrating ADC and 2DDWT for Video/Image Processing
Chin-Fa HSIEH Tsung-Han TSAI Shu-Chung YI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/03/01
Vol. E99-C  No. 3 ; pp. 415-426
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ADCpipelinediscrete wavelet transform
 Summary | Full Text:PDF(3.3MB)

A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder
Jiayi ZHU Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2612-2622
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
DBFSAOHEVCpipeline
 Summary | Full Text:PDF(4MB)

A Verification-Aware Design Methodology for Thread Pipelining Parallelization
Guo-An JIAN Cheng-An CHIEN Peng-Sheng CHEN Jiun-In GUO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/10/01
Vol. E95-D  No. 10 ; pp. 2505-2513
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
verification3D depth map generationpipelineparallel computingbehavior model
 Summary | Full Text:PDF(1.7MB)

Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling
Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 546-554
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
power gatinggate-levelpipelineself synchronousenergy minimum operationFPGA
 Summary | Full Text:PDF(4.2MB)

A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K2 K Applications
Weiwei SHEN Yibo FAN Xiaoyang ZENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 441-446
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
H.264/AVCdeblocking filterpipelineparallelism4 K2 K
 Summary | Full Text:PDF(1.8MB)

A Single Amplifier-Based 12-bit 100 MS/s 1 V 19 mW 0.13 µm CMOS ADC with Various Power and Area Minimized Circuit Techniques
Byeong-Woo KOO Seung-Jae PARK Gil-Cho AHN Seung-Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/08/01
Vol. E94-C  No. 8 ; pp. 1282-1288
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ADCpipelinelow powerSHA-freecircuit sharingtwo-step reference selection
 Summary | Full Text:PDF(2.1MB)

A 0.9-V 12-bit 40-MSPS Pipeline ADC for Wireless Receivers
Tomohiko ITO Tetsuro ITAKURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/02/01
Vol. E93-A  No. 2 ; pp. 395-401
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
A/DADCpipelinepseudodifferential amplifierI/Q sharingCMFBcommon-mode feedback
 Summary | Full Text:PDF(1.1MB)

A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers
Shinya KAJIYAMA Masamichi FUJITO Hideo KASAI Makoto MIZUNO Takanori YAMAGUCHI Yutaka SHINAGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/10/01
Vol. E92-C  No. 10 ; pp. 1258-1264
Type of Manuscript:  Special Section PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors)
Category: 
Keyword: 
flash memorymicrocontrollerdual-coreshared ROMpipelinesense amplifier
 Summary | Full Text:PDF(1.6MB)

55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers
Tomohiko ITO Daisuke KUROSE Takeshi UENO Takafumi YAMAJI Tetsuro ITAKURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/06/01
Vol. E91-C  No. 6 ; pp. 887-893
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
A/DADCpipelinelow poweramplifierpseudo-differential amplifierI/Q sharing
 Summary | Full Text:PDF(970.9KB)

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer
Takeshi KUMAKI Yasuto KURODA Masakatsu ISHIZAKI Tetsushi KOIDE Hans Jurgen MATTAUSCH Hideyuki NODA Katsumi DOSAKA Kazutami ARIMOTO Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1 ; pp. 334-345
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
content addressable memoryCAMHuffman codingparallel processingpipelinecode word table
 Summary | Full Text:PDF(2.1MB)

Low-Power Design of 10-bit 80-MSPS Pipeline ADCs
Tomohiko ITO Daisuke KUROSE Takeshi UENO Takafumi YAMAJI Tetsuro ITAKURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/07/01
Vol. E89-A  No. 7 ; pp. 2003-2008
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
analog-to-digital converterpipelineamplifier sharing
 Summary | Full Text:PDF(1.1MB)

Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use
Masao HOTTA Tatsuji MATSUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 664-672
Type of Manuscript:  INVITED PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
analog-to-digital converterADCpipelinetime-interleavingself-calibration and look-ahead pipeline
 Summary | Full Text:PDF(1.5MB)

A 10b 100 MS/s 1.4 mm2 56 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors
Byoung-Han MIN Young-Jae CHO Hee-Sung CHAE Hee-Won PARK Seung-Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/05/01
Vol. E89-C  No. 5 ; pp. 630-635
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ADCCMOSlow poweron-chip referencespipeline
 Summary | Full Text:PDF(1.3MB)

New Radix-2 to the 4th Power Pipeline FFT Processor
Jung-Yeol OH Myoung-Seob LIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C  No. 8 ; pp. 1740-1746
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category: 
Keyword: 
FFTradixpipelineSDFCSDmultiplier
 Summary | Full Text:PDF(895.1KB)

Speculative Branch Folding for Pipelined Processors
Sang-Hyun PARK Sungwook YU Jung-Wan CHO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/05/01
Vol. E88-D  No. 5 ; pp. 1064-1066
Type of Manuscript:  LETTER
Category: Computer Systems
Keyword: 
branch foldingspeculativeembedded processorpipeline
 Summary | Full Text:PDF(409.4KB)

An 8b 220 MS/s 0.25 µm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References
Young-Jae CHO Hyuen-Hee BAE Seung-Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 768-772
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ADCon-chip referencepipelineRC filterwideband SHA
 Summary | Full Text:PDF(1.3MB)

An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36 M Polygons/s FPU
Fumio ARAKAWA Motokazu OZAWA Osamu NISHII Toshihiro HATTORI Takeshi YOSHINAGA Tomoichi HAYASHI Yoshikazu KIYOSHIGE Takashi OKADA Masakazu NISHIBORI Tomoyuki KODAMA Tatsuya KAMEI Makoto ISHIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3068-3074
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
embedded processorarchitectureFPUpipeline
 Summary | Full Text:PDF(2MB)

Design of a Fast Asynchronous Embedded CISC Microprocessor, A8051
Je-Hoon LEE YoungHwan KIM Kyoung-Rok CHO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 527-534
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
asynchronousembedded-controllerCISCpipelinehandshakecompletion signal
 Summary | Full Text:PDF(1.3MB)

On Practical Implementation of the PIC Algorithm in Asynchronous CDMA Systems
Young Wha KIM Sung Ho CHO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/08/01
Vol. E86-B  No. 8 ; pp. 2508-2511
Type of Manuscript:  LETTER
Category: Wireless Communication Technology
Keyword: 
CDMAinterferencecancellationpipeline
 Summary | Full Text:PDF(698KB)

A Pipeline Structure for High-Speed Step-by-Step RS Decoding
Tung-Chou CHEN Che-Ho WEI Shyue-Win WEI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/02/01
Vol. E86-B  No. 2 ; pp. 847-849
Type of Manuscript:  LETTER
Category: Fundamental Theories
Keyword: 
Reed-Solomon codesstep-by-step decodingpipelinehigh-speed transmission systems
 Summary | Full Text:PDF(169.1KB)

Data Transfer Time by HTTP 1.0/1.1 on Asymmetric Networks Composed of Satellite and Terrestrial Links
Hiroyasu OBATA Kenji ISHIDA Junichi FUNASAKA Kitsutaro AMANO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2002/12/01
Vol. E85-B  No. 12 ; pp. 2895-2903
Type of Manuscript:  PAPER
Category: Internet
Keyword: 
web data transfer timeasymmetric networkssatellite linksterrestrial linkspipeline
 Summary | Full Text:PDF(652.5KB)

Pipelined Simple Matching for Input Buffered Switches
Man-Soo HAN Bongtae KIM 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2002/11/01
Vol. E85-B  No. 11 ; pp. 2539-2543
Type of Manuscript:  LETTER
Category: Antenna and Propagation
Keyword: 
input buffered switchpipelinecell schedulingmatching algorithm
 Summary | Full Text:PDF(371.5KB)

A 3.2-mA 6-Bit Pipelined A/D Coverter for a Bluetooth RF Transceiver
Tatsuji MATSUURA Junya KUDOH Eiki IMAIZUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8 ; pp. 1538-1545
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance Analog Integrated Circuits)
Category: 
Keyword: 
A/D converterCMOSlow powerpipelineBluetooth
 Summary | Full Text:PDF(1MB)

A Pipelined Maximal-Sized Matching Scheme for High-Speed Input-Buffered Switches
Eiji OKI Roberto ROJAS-CESSA H. Jonathan CHAO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2002/07/01
Vol. E85-B  No. 7 ; pp. 1302-1311
Type of Manuscript:  PAPER
Category: Switching
Keyword: 
schedulingpipelineinput buffered switchmaximal-sized matching
 Summary | Full Text:PDF(1.3MB)

High-Level Synthesis of Pipelined Circuits from Modular Queue-Based Specifications
Maria-Cristina MARINESCU Martin RINARD 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2655-2664
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High Level Synthesis
Keyword: 
asynchronousmodularpipelineterm rewriting system
 Summary | Full Text:PDF(276.2KB)

Parallel Test Structure in Latch Based Asynchronous Pipeline
Jing-ling YANG Chiu-sing CHOY Cheong-Fat CHAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2527-2529
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
asynchronouspipelineevent logiclatchtest
 Summary | Full Text:PDF(468.5KB)

Invariant-Free Formal Verification of Pipelined and Superscalar Controls by Behavior-Covering and Partial Unfolding
Toru SHONAI Tsuguo SHIMIZU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/02/25
Vol. E82-D  No. 2 ; pp. 376-388
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
formal verificationprocessorpipelinesuperscalar
 Summary | Full Text:PDF(2MB)

Design Optimization by Using Flexible Pipelined Modules
Masahiro FUKUI Masakazu TANAKA Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2521-2528
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Optimization
Keyword: 
pipelinedesign tuningmodule generation
 Summary | Full Text:PDF(648.9KB)

Proposal for Incremental Formal Verification
Toru SHONAI Kazuhiko MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/11/25
Vol. E81-D  No. 11 ; pp. 1172-1185
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
formal verificationprocessorpipelineBDDtheorem prover
 Summary | Full Text:PDF(1.1MB)

Technology Issues on Superconducting Digital Communication Circuits and Systems
Shinichi YOROZU Yoshihito HASHIMOTO Shuichi TAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/10/25
Vol. E81-C  No. 10 ; pp. 1601-1607
Type of Manuscript:  INVITED PAPER (Special Issue on Low- and High-Temperature Superconductive Electron Devices and Their Applications)
Category: Digital Applications
Keyword: 
superconductornetworkpipelineringcommunication
 Summary | Full Text:PDF(921.8KB)

SEWD: A Cache Architecture to Speed up the Misaligned Instruction Prefetch
Joon-Seo YIM In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/07/25
Vol. E80-D  No. 7 ; pp. 742-745
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
cachemicroprocessorpipeline
 Summary | Full Text:PDF(303.7KB)

Formal Verification System for Pipelined Processors
Toru SHONAI Tsuguo SHIMIZU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/06/25
Vol. E79-A  No. 6 ; pp. 883-891
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
formal verificationpipelineprocessorcorrectnessmathematical induction
 Summary | Full Text:PDF(753KB)

A Supplementary Scheme for Reducing Cache Access Time
Jong-Hong BAE Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/04/25
Vol. E79-D  No. 4 ; pp. 385-387
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
computer architecturecachepenalty cyclespipeline
 Summary | Full Text:PDF(238.1KB)

Real-Time Feed-Forward Control LSIs for a Direct Wafer Exposure Electron Beam System
Hironori YAMAUCHI Tetsuo MOROSAWA Takashi WATANABE Atsushi IWATA Tsutomu HOSAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/01/25
Vol. E76-C  No. 1 ; pp. 124-135
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
asicpipelineadaptiveelectron beam
 Summary | Full Text:PDF(1.1MB)

A VLSI Processor Architecture for a Back-Propagation Accelerator
Yoshio HIROSE Hideaki ANBUTSU Koichi YAMASHITA Gensuke GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10 ; pp. 1223-1231
Type of Manuscript:  Special Section PAPER (Special Issue on Microprocessors)
Category: Application Specific Processors
Keyword: 
back-propagationgate arrayneural networkpipelineprocessor
 Summary | Full Text:PDF(642KB)