Keyword : phase-locked loop


A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display
Ho-Seong KIM Pil-Ho LEE Jin-Wook HAN Seung-Hun SHIN Seung-Wuk BAEK Doo-Ill PARK Yongkyu SEO Young-Chan JANG 
Publication:   
Publication Date: 2017/11/01
Vol. E100-C  No. 11 ; pp. 1035-1038
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
transmitter bridge chipMIPI D-PHYDSIFPGA-based frame generatorphase-locked loop
 Summary | Full Text:PDF(616.5KB)

A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design
Zule XU Takayuki KAWAHARA 
Publication:   
Publication Date: 2017/04/01
Vol. E100-C  No. 4 ; pp. 370-372
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
ring oscillatorphase-locked loopbehavioral modeldigital PLL
 Summary | Full Text:PDF(318KB)

Design of a Compact Double-Channel 5-Gb/s/ch Serializer Array for High-Speed Parallel Links
Chang-chun ZHANG Long MIAO Kui-ying YIN Yu-feng GUO Lei-lei LIU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/11/01
Vol. E97-C  No. 11 ; pp. 1104-1111
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
CMOSserializerphase-locked loopdelay-locked loopparallel links
 Summary | Full Text:PDF(3.5MB)

A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS
Sho IKEDA Sang_yeop LEE Tatsuya KAMIMURA Hiroyuki ITO Noboru ISHIHARA Kazuya MASU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/06/01
Vol. E97-C  No. 6 ; pp. 495-504
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
injection-locked frequency dividerphase-locked loopClass-C VCOCMOSlow supply voltage
 Summary | Full Text:PDF(3.1MB)

Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers
Jun Gyu LEE Zule XU Shoichi MASUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8 ; pp. 1337-1346
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
phase-locked loopfrequency synthesizerloop designsettling timeprocess variations
 Summary | Full Text:PDF(1.9MB)

Reduction of Charge Injection and Current-Mismatch Errors of Charge Pump for Phase-Locked Loop
Masahiro YOSHIOKA Nobuo FUJII 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/02/01
Vol. E92-A  No. 2 ; pp. 381-388
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
charge pumpcharge injectioncurrent-mismatchspurious noisephase-locked loop
 Summary | Full Text:PDF(630.9KB)

Deadzone-Minimized Systematic Offset-Free Phase Detectors
Young-Sang KIM Yunjae SUH Hong-June PARK Jae-Yoon SIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1525-1528
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
phase detectorphase offsetdeadzonemultiphase generationdelay-locked loopphase-locked loop
 Summary | Full Text:PDF(356.3KB)

Enhanced Entrainment of Synchronous Inverters for Distributed Power Sources
Takashi HIKIHARA Tadashi SAWADA Tsuyoshi FUNAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/11/01
Vol. E90-A  No. 11 ; pp. 2516-2525
Type of Manuscript:  PAPER
Category: Nonlinear Problems
Keyword: 
synchronizationdistributed power sourcepower systemsynchronous inverterphase-locked loop
 Summary | Full Text:PDF(2.2MB)

Amplitude Response Curves of Frequency-Locked Rotations
Yoshihiko SUSUKI Yoshisuke UEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/10/01
Vol. E90-A  No. 10 ; pp. 2250-2252
Type of Manuscript:  Special Section LETTER (Special Section on Nonlinear Theory and its Applications)
Category: Nonlinear Phenomena and Analysis
Keyword: 
phase-locked loopfrequency entrainmentrotationresponse curve
 Summary | Full Text:PDF(255.6KB)

A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation
Ching-Yuan YANG Jung-Mao LIN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/01/01
Vol. E90-C  No. 1 ; pp. 196-200
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
burst-mode CDRclock recoveryphase-locked looprealigned oscillation
 Summary | Full Text:PDF(674.9KB)

A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector
Ching-Yuan YANG Yu LEE Cheng-Hsing LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 746-752
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
phase-locked loopphase synchronizationclock and data recoveryphase detector
 Summary | Full Text:PDF(905.2KB)

A Spread-Spectrum Clock Generator Using Fractional-N PLL with an Extended Range ΣΔ Modulator
Yi-Bin HSIEH Yao-Huang KAO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 851-857
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
spread spectrumΣΔ modulatorphase-locked loopfractional-N
 Summary | Full Text:PDF(2.1MB)

The Tracking of the Optimal Operating Frequency in a Class E Backlight Inverter Using the PLL Technique
Chang Hua LIN John Yanhao CHEN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6 ; pp. 1253-1262
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: PLL
Keyword: 
backlight modulepiezoelectric transformerphase-locked looptemperature effect
 Summary | Full Text:PDF(725.6KB)

A Jitter Suppression Technique for a Clock Multiplier
Kiyoshi ISHII Keiji KISHINE Haruhiko ICHINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/04/25
Vol. E83-C  No. 4 ; pp. 647-651
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock multiplierphase-locked loopSAW filterjitter generationjitter transfer function
 Summary | Full Text:PDF(930.9KB)

Passively Mode-Locked Micromechanically-Tunable Semiconductor Lasers
Yoshitada KATAGIRI Atsushi TAKADA Shigendo NISHI Hiroshi ABE Yuji UENISHI Shinji NAGAOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/02/25
Vol. E81-C  No. 2 ; pp. 151-159
Type of Manuscript:  Special Section PAPER (Special Issue on Ultrashort Optical Pulse Technologies and their Applications)
Category: 
Keyword: 
mode-locked semiconductor laserphase-locked loopmicromechanicsexternal-cavity lasertunable optical pulse source
 Summary | Full Text:PDF(929.5KB)

A 0.18-µm CMOS Hot-Standby PLL Using a Noise-Immune Adaptive-Gain VCO
Masayuki MIZUNO Koichiro FURUTA Takeshi ANDOH Akira TANABE Takao TAMURA Hidenobu MIYAMOTO Akio FURUKAWA Masakazu YAMASHINA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12 ; pp. 1560-1571
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
phase-locked looplow voltagelow jitterfast-lock time
 Summary | Full Text:PDF(974.5KB)