Keyword : performance optimization


Cooperative Path Selection Framework for Effective Data Gathering in UAV-Aided Wireless Sensor Networks
Sotheara SAY Mohamad Erick ERNAWAN Shigeru SHIMAMOTO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2016/10/01
Vol. E99-B  No. 10 ; pp. 2156-2167
Type of Manuscript:  Special Section PAPER (Special Section on Satellite Communication Technologies in Conjunction with Main Topics of JC-SAT2015)
Category: 
Keyword: 
cooperative communicationdata acquisitiondata clusteringpath selection frameworkperformance optimizationwireless sensor networksunmanned aerial vehicle
 Summary | Full Text:PDF(3.5MB)

Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
Juinn-Dar HUANG Chia-I CHEN Wan-Ling HSU Yen-Ting LIN Jing-Yang JOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/02/01
Vol. E95-A  No. 2 ; pp. 559-566
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Behavioral synthesisdistributed register-fileperformance optimizationlow-powerresource bindingscheduling
 Summary | Full Text:PDF(2MB)

Performance Optimization of Time Delay Estimation Based on Chirp Spread Spectrum Using ESPRIT
Seong-Hyun JANG Yeong-Sam KIM Sang-Hoon YOON Jong-Wha CHONG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2011/02/01
Vol. E94-B  No. 2 ; pp. 607-609
Type of Manuscript:  LETTER
Category: Sensing
Keyword: 
time delay estimationperformance optimizationchirp spread spectrum
 Summary | Full Text:PDF(301KB)

DAC: A Device-Aware Cache Management Algorithm for Heterogeneous Mobile Storage Systems
Young-Jin KIM Jihong KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/12/01
Vol. E91-D  No. 12 ; pp. 2818-2833
Type of Manuscript:  PAPER
Category: System Programs
Keyword: 
heterogeneous mobile storageperformance optimizationdevice-aware cache managementdynamic cache partitioningworkload-aware management
 Summary | Full Text:PDF(512.3KB)

Increase in Delay Uncertainty by Performance Optimization
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2799-2802
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Analysis
Keyword: 
performance optimizationdelay increasestatistical timing analysisdelay uncertaintytransistor sizing
 Summary | Full Text:PDF(297.5KB)

A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2558-2568
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Performance Optimization
Keyword: 
statistical static timing analysisstatic timing analysisgate resizingtransistor sizingperformance optimization
 Summary | Full Text:PDF(418.4KB)

A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency
Katsuya SHINOHARA Norimasa OHTSUKI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2356-2365
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
performance optimizationclock frequency tuningpipelined ASIPsHW/SW co-design
 Summary | Full Text:PDF(729.6KB)

A performance-Oriented Simultaneous Placement and Global Routing Algorithm for Transport-Processing FPGAs
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1795-1806
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAtransport processinglayout designplacement and routingperformance optimizationcircuit delay
 Summary | Full Text:PDF(897.8KB)

A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for FPGAs with Path Delay Constraints
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3 ; pp. 321-329
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
FPGAtechnology mappinglayoutpath delayperformance optimization
 Summary | Full Text:PDF(714.2KB)