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Achieving Maximum Performance for Bus-Invert Coding with Time-Splitting Transmitter Circuit
Myungchul YOON
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12
pp. 2357-2363
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
low-power design,
VLSI design,
bus-invert coding,
performance analysis,
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Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip
Yue QIAN
Zhonghai LU
Wenhua DOU
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A
No. 12
pp. 3211-3220
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword:
delay bounds,
performance analysis,
network calculus,
network-on-chip,
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Worst Case Performance Analysis and Simulation of MPLS with a GPS-Based Packet Scheduler
Ling-Chih KAO
Zsehong TSAI
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Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2004/08/01
Vol. E87-B
No. 8
pp. 2308-2318
Type of Manuscript: PAPER
Category: Internet
Keyword:
MPLS,
GPS,
VPN,
performance analysis,
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Steady-State Performance Analysis of MPLS Label Switching
Ling-Chih KAO
Zsehong TSAI
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Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2001/08/01
Vol. E84-B
No. 8
pp. 2279-2291
Type of Manuscript: PAPER
Category: Internet
Keyword:
flow,
MPLS,
performance analysis,
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Performance Analysis of Flow-Based Label Switching: The Single IP Flow Model
Ling-Chih KAO
Zsehong TSAI
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Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2000/07/20
Vol. E83-B
No. 7
pp. 1417-1425
Type of Manuscript: PAPER
Category: Fiber-Optic Transmission
Keyword:
flow,
label switch,
performance analysis,
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