IEICE SEARCH SYSTEM

Keyword : partitioning

Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors Hasitha Muthumala WAIDYASOORIYA Yosuke OHBAYASHI Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 354-363 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: memory allocation, partitioning, reconfigurable processors,
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A Fast IP Address Lookup Algorithm Based on Search Space Reduction Hyuntae PARK Hyunjin KIM Hong-Sik KIM Sungho KANG
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2010/04/01 Vol. E93-B No. 4 pp. 1009-1012 Type of Manuscript: LETTER Category: Switching for Communications Keyword: IP address lookup, search space reduction, partitioning,
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Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming Ki-Yong AHN Chong-Min KYUNG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/09/01 Vol. E92-A No. 9 pp. 2318-2325 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: system on chip, low power design, partitioning, integer linear programming,
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Thermal-Aware Placement Based on FM Partition Scheme and Force-Directed Heuristic Jing LI Hiroshi MIYASHITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 989-995 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: VLSI circuit physical design, thermal placement, partitioning, reliability, force-directed algorithm,
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An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs Yuichi NAKAMURA Ko YOSHIKAWA Takeshi YOSHIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3351-3357 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: logic design, engineering change orders, partitioning,
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A Hierarchical Cost Estimation Technique for High Level Synthesis Mahmoud MERIBOUT Masato MOTOMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/02/01 Vol. E86-A No. 2 pp. 444-461 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: high level synthesis, hardware cost estimation, multiplexer-based architecture, bus-based architecture, scheduling, allocation, partitioning,
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A Hierarchical Circuit Clustering Algorithm with Stable Performance Seung-June KYOUNG Kwang-Su SEONG In-Cheol PARK Chong-Min KYUNG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/09/20 Vol. E82-A No. 9 pp. 1987-1993 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: VLSI, CAD, partitioning, clustering,
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A Fault-Tolerant Deadlock-Free Multicast Algorithm for Wormhole Routed Hypercubes Shih-Chang WANG Jeng-Ping LIN Sy-Yen KUO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/03/20 Vol. E82-D No. 3 pp. 677-686 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: fault tolerance, wormhole routing, hypercube, multicast, partitioning,
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A Balanced-Mesh Clock Routing Technique for Performance Improvement Hidenori SATO Hiroaki MATSUDA Akira ONOZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/08/20 Vol. E80-A No. 8 pp. 1489-1495 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: LSI, CAD, layout design, clock skew, partitioning, routing, MPEG2,
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A New Approach of Fractal-Analysis Based Module Clustering for VLSI Placement Masahiko TOYONAGA Shih-Tsung YANG Isao SHIRAKAWA Toshiro AKINO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/20 Vol. E77-A No. 12 pp. 2045-2052 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: clustering, fractal analysis, placement, partitioning,
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