Keyword : parallelizing compiler


Power-Aware Compiler Controllable Chip Multiprocessor
Hiroaki SHIKANO Jun SHIRAKO Yasutaka WADA Keiji KIMURA Hironori KASAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 432-439
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
chip multiprocessorparallelizing compilerfrequency and voltage control
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Development and Implementation of an Interactive Parallelization Assistance Tool for OpenMP: iPat/OMP
Makoto ISHIHARA Hiroki HONDA Mitsuhisa SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/02/01
Vol. E89-D  No. 2 ; pp. 399-407
Type of Manuscript:  Special Section PAPER (Special Section on Parallel/Distributed Computing and Networking)
Category: Parallel/Distributed Programming Models, Paradigms and Tools
Keyword: 
OpenMPinteractive parallelization assistance toolparallelizing compilerhuman readability
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Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis
Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3184-3191
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
HDLhigh-level synthesisparallelizing compilerbit length
 Summary | Full Text:PDF(863.4KB)

Multigrain Parallel Processing on Compiler Cooperative OSCAR Chip Multiprocessor Architecture
Keiji KIMURA Takeshi KODAKA Motoki OBATA Hironori KASAHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 570-579
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword: 
chip multiprocessormultigrain parallel processingparallelizing compiler
 Summary | Full Text:PDF(814.9KB)

Efficient Implementation of Multi-Dimensional Array Redistribution
Minyi GUO Yoshiyuki YAMASHITA Ikuo NAKATA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/11/25
Vol. E81-D  No. 11 ; pp. 1195-1204
Type of Manuscript:  PAPER
Category: Sofware System
Keyword: 
parallelizing compilerarray redistributiondistributed memory parallel computersinterprocessor communicationdata parallel language
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PPD: A Practical Parallel Loop Detector for Parallelizing Compilers on Multiprocessor Systems*
Chao-Tung YANG Cheng-Tien WU Shian-Shyong TSENG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/11/25
Vol. E79-D  No. 11 ; pp. 1545-1560
Type of Manuscript:  PAPER
Category: Sofware System
Keyword: 
parallelizing compilerdata dependence analysisdependent testsDOALL loopsDOACROSS loopsloop parallelizationI test
 Summary | Full Text:PDF(1.2MB)