Keyword : parallel processing


Hybrid Parallel Implementation of Inverse Matrix Computation by SMW Formula for Interactive Simulation
Shotaro IWANAGA  Shinji FUKUMA  Shin-ichiro MORI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12  pp. 2952-2953
Type of Manuscript: Special Section LETTER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
interactive simulationlinear equation solverSMW formulaparallel processingreal-time processing
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Analysis of Parallel Decodable Turbo Codes
Orhan GAZ 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2012/05/01
Vol. E95-B  No. 5  pp. 1584-1591
Type of Manuscript: PAPER
Category: Fundamental Theories for Communications
Keyword: 
Turbo codesmemory collisionparallel processing
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Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster
Junichi OHMURA  Takefumi MIYOSHI  Hidetsugu IRIE  Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/12/01
Vol. E94-D  No. 12  pp. 2319-2327
Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
parallel processingmulti-core processorGPUcomputation-communication overlap
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NSIM: An Interconnection Network Simulator for Extreme-Scale Parallel Computers
Hideki MIWA  Ryutaro SUSUKITA  Hidetomo SHIBAMURA  Tomoya HIRAO  Jun MAKI  Makoto YOSHIDA  Takayuki KANDO  Yuichiro AJIMA  Ikuo MIYOSHI  Toshiyuki SHIMIZU  Yuji OINAGA  Hisashige ANDO  Yuichi INADOMI  Koji INOUE  Mutsumi AOYAGI  Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/12/01
Vol. E94-D  No. 12  pp. 2298-2308
Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
discrete event simulationmultiprocessor interconnectionparallel processing
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Optimized Implementation of Pedestrian Tracking Using Multiple Cues on GPU
Ryusuke MIYAMOTO  Hiroki SUGANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11  pp. 2323-2333
Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Image Processing
Keyword: 
pedestrian trackingGPU implementationparallel processingparticle filter
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NUFFT- & GPU-Based Fast Imaging of Vegetation
Amedeo CAPOZZOLI  Claudio CURCIO  Antonio DI VICO  Angelo LISENO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2011/07/01
Vol. E94-B  No. 7  pp. 2092-2103
Type of Manuscript: PAPER
Category: Sensing
Keyword: 
imaging of vegetationNon-Uniform FFT (NUFFT)Graphics Processing Unit (GPU)parallel processingFiltered Backprojection (FBP)radon transform inversionCUDApolarimetrictemporal decorrelationindoor setup
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A Fast Divide-and-Conquer Algorithm for Indexing Human Genome Sequences
Woong-Kee LOH  Yang-Sae MOON  Wookey LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/07/01
Vol. E94-D  No. 7  pp. 1369-1377
Type of Manuscript: PAPER
Category: Fundamentals of Information Systems
Keyword: 
human genome sequencesindexingsuffix treememory bottleneck problemdivide-and-conquerparallel processing
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Energy-Saving Stochastic Scheduling of a Real-Time Parallel Task with Varying Computation Amount on Multi-Core Processors
Wan Yeon LEE  Kyong Hoon KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/02/01
Vol. E94-A  No. 2  pp. 842-845
Type of Manuscript: LETTER
Category: Systems and Control
Keyword: 
multi-coreenergyschedulingreal-time taskparallel processing
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High-Speed Computation of the Kleene Star in Max-Plus Algebraic System Using a Cell Broadband Engine
Hiroyuki GOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/07/01
Vol. E93-D  No. 7  pp. 1798-1806
Type of Manuscript: PAPER
Category: Fundamentals of Information Systems
Keyword: 
directed acyclic graphmax-plus algebraschedulingparallel processingvector processingCell Broadband Engine
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An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit
Yuji OKAZAKI  Takanori UNO  Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C  No. 6  pp. 827-834
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
EMIcommon-mode currentoptimization algorithmECUparallel processing
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Hamiltonian Cycles and Hamiltonian Paths in Faulty Burnt Pancake Graphs
Keiichi KANEKO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/04/01
Vol. E90-D  No. 4  pp. 716-721
Type of Manuscript: PAPER
Category: Algorithm Theory
Keyword: 
signed permutationinterconnection networkrouting algorithmparallel processing
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Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer
Takeshi KUMAKI  Yasuto KURODA  Masakatsu ISHIZAKI  Tetsushi KOIDE  Hans Jurgen MATTAUSCH  Hideyuki NODA  Katsumi DOSAKA  Kazutami ARIMOTO  Kazunori SAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1  pp. 334-345
Type of Manuscript: PAPER
Category: Image Processing and Video Processing
Keyword: 
content addressable memoryCAMHuffman codingparallel processingpipelinecode word table
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Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory
Takeshi KUMAKI  Yutaka KONO  Masakatsu ISHIZAKI  Tetsushi KOIDE  Hans Jurgen MATTAUSCH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1  pp. 346-354
Type of Manuscript: PAPER
Category: Image Processing and Video Processing
Keyword: 
multiportcontent addressable memoryCAMparallel processingSIMDcategorizationbit parallel block paralleltable-lookup-codingHuffman coding
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A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing
Junichi MIYAKOSHI  Yuichiro MURACHI  Tomokazu ISHIHARA  Hiroshi KAWAGUCHI  Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11  pp. 1629-1636
Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
SRAMlow powerparallel processingimage signal processingH.264MPEG
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Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation
Takashi MORIMOTO  Hidekazu ADACHI  Osamu KIRIYAMA  Tetsushi KOIDE  Hans Jurgen MATTAUSCH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3  pp. 1299-1302
Type of Manuscript: LETTER
Category: Image Processing and Video Processing
Keyword: 
image segmentationreal-time image processingparallel processingLSI implementation
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Entropy Based Evaluation of Communication Predictability in Parallel Applications
Alex K. JONES  Jiang ZHENG  Ahmed AMER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/02/01
Vol. E89-D  No. 2  pp. 469-478
Type of Manuscript: Special Section PAPER (Special Section on Parallel/Distributed Computing and Networking)
Category: Performance Evaluation
Keyword: 
predictioncommunicationparallel processingentropyperformancecircuit switching
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A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers
Xizhen XU  Sotirios G. ZIAVRAS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/02/01
Vol. E89-D  No. 2  pp. 639-646
Type of Manuscript: Special Section PAPER (Special Section on Parallel/Distributed Computing and Networking)
Category: Parallel/Distributed Algorithms
Keyword: 
configurable computingFPGASIMDparallel processingmemory switchingFFThardware-software codesign
  Summary |  Full Text:PDF

A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era
Kazutoshi KOBAYASHI  Masao ARAMOTO  Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4  pp. 552-558
Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
parallel processingVLIWSMTlow powernanometerleakage power
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Performance Evaluation of Duplication Based Scheduling Algorithms in Multiprocessor Systems
Gyung-Leen PARK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/11/01
Vol. E86-A  No. 11  pp. 2797-2801
Type of Manuscript: Special Section LETTER (Special Section on Concurrent System Technology)
Category: 
Keyword: 
task graphmultiprocessor schedulingstochastic Petri netparallel processing
  Summary |  Full Text:PDF

ReVolver/C40: A Scalable Parallel Computer for Volume Rendering--Design and Implementation--
Shin-ichiro MORI  Tomoaki TSUMURA  Masahiro GOSHIMA  Yasuhiko NAKASHIMA  Hiroshi NAKASHIMA  Shinji TOMITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10  pp. 2006-2015
Type of Manuscript: Special Section PAPER (Special Issue on Development of Advanced Computer Systems)
Category: 
Keyword: 
volume renderingparallel processingscalable architecturevisualization
  Summary |  Full Text:PDF

The Development of the Earth Simulator
Shinichi HABATA  Mitsuo YOKOKAWA  Shigemune KITAWAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10  pp. 1947-1954
Type of Manuscript: INVITED PAPER (Special Issue on Development of Advanced Computer Systems)
Category: 
Keyword: 
supercomputerHPC (high performance computing)parallel processingshared memoryvector processorcrossbar network
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Dynamic Equations of Generalized Eigenvalue Problems
Yao-Lin JIANG  Richard M. M. CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/08/01
Vol. E85-A  No. 8  pp. 1974-1978
Type of Manuscript: LETTER
Category: Numerical Analysis and Optimization
Keyword: 
generalized eigenvalue problemsoptimization techniquesdynamic equationsparallel processingengineering applications
  Summary |  Full Text:PDF

Dynamically Programmable Parallel Processor (DPPP): A Novel Reconfigurable Architecture with Simple Program Interface
Boon-Keat TAN  Ryuji YOSHIMURA  Toshimasa MATSUOKA  Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/11/01
Vol. E84-D  No. 11  pp. 1521-1527
Type of Manuscript: Special Section PAPER (Special Issue on Function Integrated Information Systems)
Category: 
Keyword: 
CDMA busparallel processinginterconnection topologyrouting flexibilityfault tolerant
  Summary |  Full Text:PDF

A Novel Dynamically Programmable Arithmetic Array (DPAA) Processor for Digital Signal Processing
Boon-Keat TAN  Ryuji YOSHIMURA  Toshimasa MATSUOKA  Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/03/01
Vol. E84-A  No. 3  pp. 741-747
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
DPAADSPparallel processinginterconnection topologyrouting flexibility
  Summary |  Full Text:PDF

Adaptive Image Enhancement Algorithms and Their Implementation for Real-Time Video Signals
Ichiro KURODA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/02/01
Vol. E84-A  No. 2  pp. 390-399
Type of Manuscript: TUTORIAL PAPER
Category: 
Keyword: 
image enhancement2-D filteringfast algorithmparallel processingmicroprocessor
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Programmable Dataflow Computing on PCA
Norbert IMLIG  Tsunemichi SHIOZAWA  Ryusuke KONISHI  Kiyoshi OGURI  Kouichi NAGAMI  Hideyuki ITO  Minoru INAMORI  Hiroshi NAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/20
Vol. E83-A  No. 12  pp. 2409-2416
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
programmable logic devicesdataflow computingparallel processingplastic cell architecture
  Summary |  Full Text:PDF

A Parallel Approach for Computing Complex Eigenvalue Problems
Yao-Lin JIANG  Richard M. M. CHEN  Zu-Lan HUANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/10/20
Vol. E83-A  No. 10  pp. 2000-2008
Type of Manuscript: PAPER
Category: Numerical Analysis and Optimization
Keyword: 
complex eigenvalue problemsoptimizationdynamic equationswaveform relaxationparallel processing
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Addition of Integers in a Computer Memory: Information Theory Approach
Vladimir B. BALAKIRSKY 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/10/20
Vol. E83-A  No. 10  pp. 1929-1935
Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Code for Computer Memory
Keyword: 
encodingdecodingmulti-user communicationadditionparallel processing
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Parallelizing SDP (Sum of Disjoint Products) Algorithms for Fast Reliability Analysis
Tatsuhiro TSUCHIYA  Tomoya KAJIKAWA  Tohru KIKUNO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/20
Vol. E83-D  No. 5  pp. 1183-1186
Type of Manuscript: LETTER
Category: Fault Tolerance
Keyword: 
network reliabilitynetworks of workstationsdependability evaluationparallel processingcoherent systems
  Summary |  Full Text:PDF

Efficient Broadcasting in an Arrangement Graph Using Multiple Spanning Trees
Yuh-Shyan CHEN  Tong-Ying JUANG  En-Huai TSENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/01/20
Vol. E83-A  No. 1  pp. 139-149
Type of Manuscript: PAPER
Category: Graphs and Networks
Keyword: 
arrangement graphbroadcastinterconnection networkparallel processingrouting
  Summary |  Full Text:PDF

Pattern Formation in Reaction-Diffusion Enzyme Transistor Circuits
Masahiko HIRATSUKA  Takafumi AOKI  Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/09/20
Vol. E82-A  No. 9  pp. 1809-1817
Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: 
Keyword: 
molecular computingmolecular devicesreaction-diffusion dynamicspattern formationnonlinear signal processingparallel processing
  Summary |  Full Text:PDF

Iterative Methods for Dense Linear Systems on Distributed Memory Parallel Computers
Muneharu YOKOYAMA  Takaomi SHIGEHARA  Hiroshi MIZOGUCHI  Taketoshi MISHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/20
Vol. E82-A  No. 3  pp. 483-486
Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
iterative methods for solving dense linear systemsconjugate gradient methodconjugate residual methodparallel processingdistributed memory parallel computers
  Summary |  Full Text:PDF

Viewpoint-Based Similarity Discernment on SNAP
Takashi YUKAWA  Sanda M. HARABAGIU  Dan I. MOLDOVAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/02/20
Vol. E82-D  No. 2  pp. 500-502
Type of Manuscript: LETTER
Category: Artificial Intelligence and Cognitive Science
Keyword: 
semantic networkmarker propagationanalogyinference systemparallel processingnatural language processing
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System Electronics Technologies for Video Processing and Applications
Tomio KISHIMOTO  Hironori YAMAUCHI  Ryota KASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/20
Vol. E82-A  No. 2  pp. 197-205
Type of Manuscript: INVITED PAPER (Special Section on VLSI for Digital Signal Processing)
Category: 
Keyword: 
video processingMPEG2parallel processingVLSI processor architecture
  Summary |  Full Text:PDF

5. 4 GOPS, 81 GB/s Linear Array Architecture DSP
Akihiko HASHIGUCHI  Masuyoshi KUROKAWA  Ken'ichiro NAKAMURA  Hiroshi OKUDA  Koji AOYAMA  Mitsuharu OHKI  Katsunori SENO  Ichiro KUMATA  Masatoshi AIKAWA  Hirokazu HANAKI  Takao YAMAZAKI  Mitsuo SONEDA  Seiichiro IWASE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/20
Vol. E81-C  No. 5  pp. 661-668
Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
videoparallel processingSIMDDSP
  Summary |  Full Text:PDF

Optical Flow Detection System Using a Parallel Processor NEURO4
Jun TAKEDA  Ken-ichi TANAKA  Kazuo KYUMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/03/20
Vol. E81-A  No. 3  pp. 439-445
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
optical flowmoving image recognitionneural networkparallel processingSIMD
  Summary |  Full Text:PDF

Accuracy of the Minimum Time Estimate for Programs on Heterogeneous Machines
Dingchao LI  Yuji IWAHORI  Naohiro ISHII 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/01/20
Vol. E81-D  No. 1  pp. 19-26
Type of Manuscript: PAPER
Category: Computer Systems
Keyword: 
parallel processingheterogeneous machines compile-time schedulingdirected acyclic graphslower time bounds
  Summary |  Full Text:PDF

CORErouter-I: An Experimental Parallel IP Router Using a Cluster of Workstations
Mitsuru MARUYAMA  Naohisa TAKAHASHI  Takeshi MIEI  Tsuyoshi OGURA  Tetsuo KAWANO  Satoru YAGI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1997/10/20
Vol. E80-B  No. 10  pp. 1407-1414
Type of Manuscript: Special Section PAPER (Special Issue on Network Interworking)
Category: System architecture
Keyword: 
internetrouterTCP/IPparallel processingworkstation clusterrouting protocol
  Summary |  Full Text:PDF

Special-Purpose Hardware Architecture for Large Scale Linear Programming
Shinhaeng LEE  Shin'ichiro OMACHI  Hirotomo ASO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/09/20
Vol. E80-D  No. 9  pp. 893-898
Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Computer Architecture
Keyword: 
parallel processingsystolic arraysspecial-purpose hardwarelinear programmingrevised simplex method
  Summary |  Full Text:PDF

Design and Analysis of Multiwave Interconnection Networks for MCM-Based Parallel Processing
Takafumi AOKI  Shinichi SHIONOYA  Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/20
Vol. E80-C  No. 7  pp. 935-940
Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Novel Concept Devices
Keyword: 
parallel processinginterconnection networksmessage-passing multiprocessor systemsmultichip module (MCM)optical interconnections
  Summary |  Full Text:PDF

A 3.2 GFLOPS Neural Network Accelerator
Shinji KOMORI  Yutaka ARIMA  Yoshikazu KONDO  Hirono TSUBOTA  Ken-ichi TANAKA  Kazuo KYUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/20
Vol. E80-C  No. 7  pp. 859-867
Type of Manuscript: INVITED PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: 
Keyword: 
neural networkparallel processingSIMDLSI
  Summary |  Full Text:PDF

A Lookahead Heuristic for Heterogeneous Multiprocessor Scheduling with Communication Costs
Dingchao LI  Akira MIZUNO  Yuji IWAHORI  Naohiro ISHII 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/04/20
Vol. E80-D  No. 4  pp. 489-494
Type of Manuscript: Special Section PAPER (Special Issue on Parallel and Distributed Supercomputing)
Category: 
Keyword: 
parallel processingheterogeneous multiprocessorstask graphscommunication costsscheduling heuristics
  Summary |  Full Text:PDF

Design of Array Processors for 2-D Discrete Fourier Transform
Shietung PENG  Igor SEDUKHIN  Stanislav SEDUKHIN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/04/20
Vol. E80-D  No. 4  pp. 455-465
Type of Manuscript: Special Section PAPER (Special Issue on Parallel and Distributed Supercomputing)
Category: 
Keyword: 
algorithm mapping2-dimensional discrete Fourier transformparallel processingsystolic array processorsVLSI architectures
  Summary |  Full Text:PDF

Parallel mB1C Word Alignment Procedure and Its Performance for High-Speed Optical Transmission
Yoshihiko UEMATSU  Koichi MURATA  Shinji MATSUOKA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1997/03/20
Vol. E80-B  No. 3  pp. 476-482
Type of Manuscript: PAPER
Category: Communication Systems and Transmission Equipment
Keyword: 
mBlC codeDmB1M codeword alignmentparallel processingsignal flow graph
  Summary |  Full Text:PDF

Parallel Genetic Algorithm for Constrained Clustering
Myung-Mook HAN  Shoji TATSUMI  Yasuhiko KITAMURA  Takaaki OKUMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/02/20
Vol. E80-A  No. 2  pp. 416-422
Type of Manuscript: LETTER
Category: Modeling and Simulation
Keyword: 
parallel processingGenetic Algorithmmultiprocessorconstrained clustering
  Summary |  Full Text:PDF

A Highly Parallel Systolic Tridiagonal Solver
Takashi NARITOMI  Hirotomo ASO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/09/20
Vol. E79-D  No. 9  pp. 1241-1247
Type of Manuscript: PAPER
Category: Computer Systems
Keyword: 
scientific computingparallel processingparallel algorithmtridiagonal linear systemsystolic array
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Performance Analysis of Parallel Test Generation for Combinational Circuits
Tomoo INOUE  Takaharu FUJII  Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/09/20
Vol. E79-D  No. 9  pp. 1257-1265
Type of Manuscript: PAPER
Category: Fault Tolerant Computing
Keyword: 
test generationparallel processingperformance analysisinterprocessor communicationspeedup
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Parallel Genetic Algorithms Based on a Multiprocessor System FIN and Its Application
Myung-Mook HAN  Shoji TATSUMI  Yasuhiko KITAMURA  Takaaki OKUMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/11/20
Vol. E78-A  No. 11  pp. 1595-1605
Type of Manuscript: PAPER
Category: Algorithms and Data Structures
Keyword: 
parallel processinggenetic algorithmmultiprocessortraveling salesman problem
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Parallel Processing Techniques for Multidimensional Sampling Lattice Alteration Based on Overlap-Add and Overlap-Save Methods
Shogo MURAMATSU  Hitoshi KIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/08/20
Vol. E78-A  No. 8  pp. 934-943
Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
multidimensional signal processingmultirate signal processingparallel processingoverlap-add/save method
  Summary |  Full Text:PDF

A Declarative Synchronization Mechanism for Parallel Object-Oriented Computation
Takanobu BABA  Norihito SAITOH  Takahiro FURUTA  Hiroshi TAGUCHI  Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/08/20
Vol. E78-D  No. 8  pp. 969-981
Type of Manuscript: PAPER
Category: Computer Systems
Keyword: 
parallel processingdistributed processingsynchronization mechanismparallel object-oriented computationasynchronous operation
  Summary |  Full Text:PDF

The Optimal Routing Algorithm in Hierarchical Cubic Network and Its Properties
San-Kyun YUN  Kyu Ho PARK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/04/20
Vol. E78-D  No. 4  pp. 436-443
Type of Manuscript: PAPER
Category: Computer Networks
Keyword: 
interconnection networkhypercubehierarchical cubic network (HCN)parallel processingrouting algorithm
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High-Level Synthesis of a Multithreaded Processor for Image Generation
Takao ONOYE  Toshihiro MASAKI  Isao SHIRAKAWA  Hiroaki HIRATA  Kozo KIMURA  Shigeo ASAHARA  Takayuki SAGISHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/20
Vol. E78-A  No. 3  pp. 322-330
Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
processormultithreadparallel processinghigh-level synthesisimage generation
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A MRF-Based Parallel Processing for Speech Recognition Using Linear Predictive HMM
Hideki NODA  Mehdi N. SHIRAZI  Mamoru NAKATSUI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/10/20
Vol. E77-D  No. 10  pp. 1142-1147
Type of Manuscript: PAPER
Category: Speech Processing
Keyword: 
parallel processingspeech recognitionMRF modelHMMICM algorithm
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Mapping QR Decomposition on Parallel Computers: A Study Case for Radar Applications
Antonio d'ACIERNO  Michele CECCARELLI  Alfonso FARINA  Alfredo PETROSINO  Luca TIMMONERI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1994/10/20
Vol. E77-B  No. 10  pp. 1264-1271
Type of Manuscript: PAPER
Category: Electronic and Radio Applications
Keyword: 
Radarsidelobe cancelerQR decompositionparallel processingsystolic arrayMIMD computersSIMD computers
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High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems
Yasuaki SAWANO  Bumchul KIM  Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/20
Vol. E77-C  No. 7  pp. 1101-1107
Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
intelligent integrated systemshigh-level synthesisparallel processingminimum latencyscheduling
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Distributed Load Balancing Schemes for Parallel Video Encoding System
Zhaochen HUANG  Yoshinori TAKEUCHI  Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/05/20
Vol. E77-A  No. 5  pp. 923-930
Type of Manuscript: PAPER
Category: Parallel/Multidimensional Signal Processing
Keyword: 
distributed load balancingconvergencevideo encodingparallel processing
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Minimizing the Data Transfer in Evaluating an Expression in a Distributed-Memory Parallel-Processing System
Hiroshi OHTA  Kousuke SAKODA  Koichiro ISHIHARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/03/20
Vol. E77-D  No. 3  pp. 288-298
Type of Manuscript: PAPER
Category: Computer Systems
Keyword: 
computer systemsalgorithmparallel processingdistributed memorydata transfer
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Pure Optical Parallel Array Logic System--An Optical Parallel Computing Architecture--
Tsuyoshi KONISHI  Jun TANIDA  Yoshiki ICHIOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/01/20
Vol. E77-C  No. 1  pp. 30-34
Type of Manuscript: Special Section PAPER (Special Issue on Optical Interconnection)
Category: 
Keyword: 
optical computingoptical interconnectionparallel processingspatial light modulatorbirefringence
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The Application of a Data-Driven Processor to Automotive Engine Control
Kenji SHIMA  Koichi MUNAKATA  Shoichi WASHINO  Shinji KOMORI  Yasuya KAJIWARA  Setsuhiro SHIMOMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/20
Vol. E76-C  No. 12  pp. 1794-1803
Type of Manuscript: Special Section PAPER (Special Issue on ASICs for Automotive Electronics)
Category: 
Keyword: 
engine controlfuel injectionmicro-processordata-driven processordata flow computerparallel processing
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Load Balancing Based on Load Coherence between Continuous Images for an Object-Space Parallel Ray-Tracing System
Hiroaki KOBAYASHI  Hideyuki KUBOTA  Susumu HORIGUCHI  Tadao NAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/12/20
Vol. E76-D  No. 12  pp. 1490-1499
Type of Manuscript: PAPER
Category: Computer Systems
Keyword: 
computer systemscomputer graphicsparallel processingmultiprocessor systemsload balancing
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Satellite Image Processing System Utilizing an Extended Cellular Array Processor
Masataka AJIRO  Hiroyuki MIYATA  Takashi KAN  Masakazu SOGA  Makoto ONO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/10/20
Vol. E76-D  No. 10  pp. 1199-1207
Type of Manuscript: Special Section PAPER (Special Section on Machine Vision Applications)
Category: 
Keyword: 
parallel processingcellular array processorsatellite image processingSARFFT
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Design of Wave-Parallel Computing Architectures and Its Application to Massively Parallel Image Processing
Yasushi YUMINAKA  Takafumi AOKI  Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/20
Vol. E76-C  No. 7  pp. 1133-1143
Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Multiple-Valued Architectures and Systems
Keyword: 
multiple-valued logicset-valued logicparallel processingfrequency multiplexing
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Overlapped Partitioning Algorithm for the Solution of LSEs with Fixed Size Processor Array
Ben CHEN  Mahoki ONODA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/20
Vol. E76-A  No. 6  pp. 1011-1018
Type of Manuscript: PAPER
Category: Modeling and Simulation
Keyword: 
circuit simulationhigh-speed algorithmparallel processing
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A Hardware Architecture Design Methodology for Hidden Markov Model Based Recognition Systems Using Parallel Processing
Jun-ichi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/20
Vol. E76-A  No. 6  pp. 990-1000
Type of Manuscript: PAPER
Category: Digital Signal Processing
Keyword: 
hidden markov modelspeech recognitioncorrective trainingparallel processingarray processorsystem design
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RHINE: Reconfigurable Multiprocessor System for Video CODEC
Yoshinori TAKEUCHI  Zhao-Chen HUANG  Masatomo SAEKI  Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/20
Vol. E76-A  No. 6  pp. 947-956
Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Methods and Circuits for Signal Processing
Keyword: 
parallel processingload balancingvideo CODECparallel architecturereconfigurable architecture
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Unified Scheduling of High Performance Parallel VLSI Processors for Robotics
Bumchul KIM  Michitaka KAMEYAMA  Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/20
Vol. E76-A  No. 6  pp. 904-910
Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Parallel Processor Scheduling
Keyword: 
minimum-latency architecturespecial-purpose VLSI processorparallel processingcommunication timebus interconnection network
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Optical Multiplex Computing Based on Set-Valued Logic and Its Application to Parallel Sorting Networks
Shuichi MAEDA  Takafumi AOKI  Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/20
Vol. E76-D  No. 5  pp. 605-615
Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic)
Category: Optical Logic
Keyword: 
optical computingoptoelectronic integrated circuitsset-valued logicmultiple-valued logicparallel processing
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Space Partitioning Image Processing Technique for Parallel Recursive Half Toning
Yoshinori TAKEUCHI  Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/20
Vol. E76-A  No. 4  pp. 603-612
Type of Manuscript: PAPER
Category: Digital Signal Processing
Keyword: 
parallel processingrecursive filteringdigital half toneparallel algorithmspace partitioning processing
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Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation
Makoto HONDA  Michitaka KAMEYAMA  Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/20
Vol. E76-C  No. 3  pp. 455-462
Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
multiple-valued MOS current-mode circuitresidue number systemlatencyparallel processingrobot vision
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Parallel VLSI Processors for Robotics Using Multiple Bus Interconnection Networks
Bumchul KIM  Michitaka KAMEYAMA  Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/06/20
Vol. E75-A  No. 6  pp. 712-719
Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1991 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '91))
Category: Robot Electronics
Keyword: 
minimum-delay-time architectureVLSI processor for roboticsparallel processingparallel communicationmultiple bus interconnection networks
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Presto: A Bus-Connected Multiprocessor for a Rete-Based Production System
Hideo KIKUCHI  Takashi YUKAWA  Kazumitsu MATSUZAWA  Tsutomu ISHIKAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/05/20
Vol. E75-D  No. 3  pp. 265-273
Type of Manuscript: PAPER
Category: Computer Systems
Keyword: 
bus-connected multiprocessorparallel computerparallel processingproduction systemsrule-based systemsAI architecture
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Two-Dimensional Quadrilateral Recursive Digital Filters with Parallel Structure--Synthesis and Parallel Processing--
Tsuyoshi ISSHIKI  Hiroaki KUNIEDA  Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/20
Vol. E75-A  No. 3  pp. 352-361
Type of Manuscript: Special Section PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
quadrilateral recursive filtersparallel processing
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