Keyword : parallel prefix adder


Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication
Nobutaka KITO Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 1962-1970
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
parity predictionparallel prefix adderfault securecarry-bit duplication
 Summary | Full Text:PDF(968.9KB)

Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
Taeko MATSUNAGA Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2770-2777
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword: 
parallel prefix adderarithmetic synthesisdynamic programming
 Summary | Full Text:PDF(308.7KB)