Keyword : non-volatile memory


ATSMF: Automated Tiered Storage with Fast Memory and Slow Flash Storage to Improve Response Time with Concentrated Input-Output (IO) Workloads
Kazuichi OE Mitsuru SATO Takeshi NANRI 
Publication:   
Publication Date: 2018/12/01
Vol. E101-D  No. 12 ; pp. 2889-2901
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Memory Devices
Keyword: 
hybrid storage systemdynamic random-access memorynon-volatile memoryflash storageworkload analysis
 Summary | Full Text:PDF(1.2MB)

A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories
Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2018/07/01
Vol. E101-A  No. 7 ; pp. 1045-1052
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
non-volatile memorybit-write-reducingerror-correcting codesclustering conditionsS-bit flip conditionsS-bound graphcluster graphrelaxed REC code
 Summary | Full Text:PDF(378.1KB)

Fast Persistent Heap Based on Non-Volatile Memory
Wenzhe ZHANG Kai LU Xiaoping WANG Jie JIAN 
Publication:   
Publication Date: 2017/05/01
Vol. E100-D  No. 5 ; pp. 1035-1045
Type of Manuscript:  PAPER
Category: Software System
Keyword: 
non-volatile memoryvirtual memory managerdirect access
 Summary | Full Text:PDF(1.1MB)

ARW: Efficient Replacement Policies for Phase Change Memory and NAND Flash
Xi ZHANG Xinning DUAN Jincui YANG Jingyuan WANG 
Publication:   
Publication Date: 2017/01/01
Vol. E100-D  No. 1 ; pp. 79-90
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
replacement policyNAND flashphase change memorynon-volatile memoryemerging memory technology
 Summary | Full Text:PDF(2.7MB)

A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories
Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2398-2411
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
non-volatile memorybit-write-reducingerror-correcting codesclustering conditionsS-bit flip conditionsS-bound graphcluster graphREC code
 Summary | Full Text:PDF(1.6MB)

Migration Cost Sensitive Garbage Collection Technique for Non-Volatile Memory Systems
Sang-Ho HWANG Ju Hee CHOI Jong Wook KWAK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12 ; pp. 3177-3180
Type of Manuscript:  LETTER
Category: Software System
Keyword: 
non-volatile memorygarbage collectionwear levelingmigration costupdate frequency
 Summary | Full Text:PDF(423.4KB)

Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories
Tatsuro KOJO Masashi TAWADA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12 ; pp. 2484-2493
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
non-volatile memorymaximum-writing bitserror-correcting codesDoughnut codecode expansion
 Summary | Full Text:PDF(1.6MB)

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory
Masashi TAWADA Shinji KIMURA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12 ; pp. 2494-2504
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
non-volatile memorybit-write reductionenergy reductionwrite-reduction codeerror-correcting code
 Summary | Full Text:PDF(1.5MB)

NAND Phase Change Memory with Block Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance
Koh JOHGUCHI Kasuaki YOSHIOKA Ken TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4 ; pp. 351-359
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
phase change memorynon-volatile memorystorage class memoryblock erase interfacesolid-state drive
 Summary | Full Text:PDF(2.8MB)

UStore: STT-MRAM Based Light-Weight User-Level Storage for Enhancing Performance of Accessing Persistent Data
Yong SONG Kyuho PARK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/03/01
Vol. E97-D  No. 3 ; pp. 497-509
Type of Manuscript:  PAPER
Category: Data Engineering, Web Information Systems
Keyword: 
non-volatile memorystoragepersistent dataimplementation
 Summary | Full Text:PDF(1.9MB)

An Atomistic Study on Hydrogenation Effects toward Quality Improvement of Program/Erase Cycle of MONOS-Type Memory
Akira OTAKE Keita YAMAGUCHI Katsumasa KAMIYA Yasuteru SHIGETA Kenji SHIRAISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/05/01
Vol. E94-C  No. 5 ; pp. 693-698
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
non-volatile memoryMONOSSiNfirst principles calculationcharge trap memory
 Summary | Full Text:PDF(1.1MB)

A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI
Yasue YAMAMOTO Masanori SHIRAHAMA Toshiaki KAWASAKI Ryuji NISHIHARA Shinichi SUMI Yasuhiro AGATA Hirohito KIKUKAWA Hiroyuki YAMAUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/05/01
Vol. E90-C  No. 5 ; pp. 1129-1137
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
non-volatile memorysingle poly gatedifferential cellCMOS logic processSystem-on-Chip (SoC)
 Summary | Full Text:PDF(1.2MB)

Self-Learning Analog Neural Network LSI with High-Resolution Non-Volatile Analog Memory and a Partially-Serial Weight-Update Architecture
Takashi MORIE Osamu FUJITA Kuniharu UCHIMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7 ; pp. 990-995
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Neural Networks and Chips
Keyword: 
neural networksanalog LSIfloating gate devicenon-volatile memory
 Summary | Full Text:PDF(603.6KB)