Keyword : neuron MOS transistor


A Low Temperature DC Characteristic Analysis Utilizing a Floating Gate Neuron MOS Macromodel
Tadahiro OCHIAI Hiroshi HATANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/06/01
Vol. E86-C  No. 6 ; pp. 1114-1116
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
neuron MOS transistormacromodellow temperature DC operation analysiscircuit design parameter optimization
 Summary | Full Text:PDF(236.6KB)

A Proposition on Floating Gate Neuron MOS Macromodeling for Device Fabrications
Tadahiro OCHIAI Hiroshi HATANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2485-2491
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
neuron MOS transistorneuron MOS circuitsSPICE simulationmacromodel
 Summary | Full Text:PDF(1.4MB)

A 1-V, 1-Vp-p Input Range, Four-Quadrant Analog Multiplier Using Neuron-MOS Transistors
Koichi TANNO Okihiko ISHIZUKA Zheng TANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/05/25
Vol. E82-C  No. 5 ; pp. 750-757
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
multiplierlow voltagelow powerneuron MOS transistoranalog integrated circuit
 Summary | Full Text:PDF(435KB)

Neuron-MOS Current Mirror Circuit and Its Application to Multi-Valued Logic
Jing SHEN Koichi TANNO Okihiko ISHIZUKA Zheng TANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/05/25
Vol. E82-D  No. 5 ; pp. 940-948
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications)
Category: Circuits
Keyword: 
neuron MOS transistormulti-valued logiccurrent-mode circuitcurrent mirrorcurrent comparatorthreshold detectorT-gateintegrated circuit
 Summary | Full Text:PDF(1.1MB)

The Concept of Four-Terminal Devices and Its Significance in the Implementation of Intelligent Integrated Circuits
Tadahiro OHMI Tadashi SHIBATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7 ; pp. 1032-1041
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
four-terminal deviceneuron MOS transistorbinary-multiple-analog merged hardware algorithmsintelligent intetrated circuit
 Summary | Full Text:PDF(890.3KB)