Keyword : multiplier


RSFQ 4-bit Bit-Slice Integer Multiplier
Guang-Ming TANG Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6 ; pp. 697-702
Type of Manuscript:  Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics)
Category: 
Keyword: 
multipliersingle-flux-quantum (SFQ)microprocessorsuperconducting integrated circuits
 Summary | Full Text:PDF(2MB)

An Analytical Model of AC-DC Charge Pump Voltage Multipliers
Toru TANZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/01/01
Vol. E99-C  No. 1 ; pp. 108-118
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
AC-DCcharge pumpmodelingmultiplierrectifierRF-DC
 Summary | Full Text:PDF(1.3MB)

New Current-Mode Multipliers by CNTFET-Based n-Valued Binary Converters
Mona MORADI Reza FAGHIH MIRZAEE Keivan NAVI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/01/01
Vol. E99-C  No. 1 ; pp. 100-107
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
current-mode logicmultiplierCNTFETBinary Converterhigh-order compressor
 Summary | Full Text:PDF(880.9KB)

Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process
Xizhu PENG Yuki YAMANASHI Nobuyuki YOSHIKAWA Akira FUJIMAKI Naofumi TAKAGI Kazuyoshi TAKAGI Mutsuo HIDAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3 ; pp. 188-193
Type of Manuscript:  Special Section PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
floating point unitmultiplierLSRDPSFQ circuitsuperconductive integrated circuit
 Summary | Full Text:PDF(2.2MB)

Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation
Chin-Long WEY Ping-Chang JUI Gang-Neng SUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/02/01
Vol. E97-A  No. 2 ; pp. 616-623
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
ripple carry adder (RCA)carry-lookahead adder (CLA)ripple-borrow subtractor (RBS)multiplierdivider
 Summary | Full Text:PDF(1.6MB)

DC and High-Frequency Characteristics of GaN Schottky Varactors for Frequency Multiplication
Chong JIN Dimitris PAVLIDIS Laurence CONSIDINE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/08/01
Vol. E95-C  No. 8 ; pp. 1348-1353
Type of Manuscript:  Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM 2011)
Category: GaN-based Devices
Keyword: 
Gallium NitrideSchottky diodevaractormultiplier
 Summary | Full Text:PDF(1.4MB)

Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design
Li-Rong WANG Ming-Hsien TU Shyh-Jye JOU Chung-Len LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6 ; pp. 1112-1119
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
multipliermultiply-accumulatormodified Booth encodingreconfigurablemixed-Vtstandard cell library
 Summary | Full Text:PDF(1.5MB)

High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform
Ryosuke NAKAMOTO Sakae SAKURABA Alexandre MARTINS Takeshi ONOMI Shigeo SATO Koji NAKAJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3 ; pp. 280-287
Type of Manuscript:  Special Section PAPER (Special Section on Superconducting Signal Processing Technologies)
Category: 
Keyword: 
SFQsuper-conductive circuitsFFTmultiplieradder
 Summary | Full Text:PDF(2MB)

Binary Sequence Pairs with Two-Level Correlation and Cyclic Difference Pairs
Seok-Yong JIN Hong-Yeop SONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/11/01
Vol. E93-A  No. 11 ; pp. 2266-2271
Type of Manuscript:  Special Section PAPER (Special Section on Signal Design and its Application in Communications)
Category: Sequences
Keyword: 
ideal two-level correlationcyclic difference paircycic Hadamard difference pairmultipliercirculant Hadamard matrix conjecture
 Summary | Full Text:PDF(237.3KB)

A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier
Nobutaka KITO Kensuke HANAI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/10/01
Vol. E93-D  No. 10 ; pp. 2783-2791
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
multiplierdesign for testability4-2 adder treeC-testability
 Summary | Full Text:PDF(381.2KB)

VLSI Implementation of a 44-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic
Yasuhiro TAKAHASHI Toshikazu SEKINE Michio YOKOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 2002-2006
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: 
Keyword: 
adiabatic logicmultiplierlow powertwo-phase power supply
 Summary | Full Text:PDF(431KB)

Terahertz Frequency Multiplier Operation of Two Dimensional Plasmon Resonant Photomixer
Takuya NISHIMURA Mitsuhiro HANABE Masaki MIYAMOTO Taiichi OTSUJI Eiichi SANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/07/01
Vol. E89-C  No. 7 ; pp. 1005-1011
Type of Manuscript:  Special Section PAPER (Special Section on Heterostructure Microelectronics with TWHM2005)
Category: THz Devices
Keyword: 
plasmon resonancephotomixerterahertzmultipliergrating
 Summary | Full Text:PDF(560.7KB)

A Highly Linearized CMOS Multiplier with a Controlled Tail Current Source
Kazuhiro SHOUNO Tasuku HORI Yukio ISHIBASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A  No. 6 ; pp. 1533-1539
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category: 
Keyword: 
CMOSanalogtransconductormultipliermobility
 Summary | Full Text:PDF(1MB)

Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Implementation
Jung-Yeol OH Myoung-Seob LIM 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/04/01
Vol. E89-B  No. 4 ; pp. 1425-1429
Type of Manuscript:  LETTER
Category: Devices/Circuits for Communications
Keyword: 
FFTradix-24radix-22SDFCSDmultiplier
 Summary | Full Text:PDF(875.8KB)

Multiplier Energy Reduction by Dynamic Voltage Variation
Vasily G. MOSHNYAGA Tomoyuki YAMANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3548-3553
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Circuit
Keyword: 
multiplierenergy reductiondesign techniquesvoltage scaling
 Summary | Full Text:PDF(683.2KB)

New Radix-2 to the 4th Power Pipeline FFT Processor
Jung-Yeol OH Myoung-Seob LIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C  No. 8 ; pp. 1740-1746
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category: 
Keyword: 
FFTradixpipelineSDFCSDmultiplier
 Summary | Full Text:PDF(895.1KB)

Design of Decision Diagrams with Increased Functionality of Nodes through Group Theory
Radomir S. STANKOVI Jaakko ASTOLA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/03/01
Vol. E86-A  No. 3 ; pp. 693-703
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
decision diagrambinary decision diagram (BDD)Fourier transformmultiplier
 Summary | Full Text:PDF(930.6KB)

Parallel Evolutionary Design of Constant-Coefficient Multipliers
Dingjun CHEN Takafumi AOKI Naofumi HOMMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/02/01
Vol. E85-A  No. 2 ; pp. 508-512
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
evolutionary graph generationmultiplierPC clusterscanonical signed-digit (CSD) number representation
 Summary | Full Text:PDF(718.4KB)

Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System
Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 288-296
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
pass-transistor networkfunctional pass gateprecharge-evaluate logicmultipliersigned-digit adder
 Summary | Full Text:PDF(1.6MB)

An Area-Effective Datapath Architecture for Embedded Microprocessors and Scalable Systems
Toshiaki INOUE Takashi MANABE Sunao TORII Satoshi MATSUSHITA Masato EDAHIRO Naoki NISHI Masakazu YAMASHINA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/08/01
Vol. E84-C  No. 8 ; pp. 1014-1020
Type of Manuscript:  INVITED PAPER (Special Issue on Silicon Nanodevices)
Category: 
Keyword: 
SIMDmultiplierembedded microprocessoron-chip multiprocessorarea-efficiency
 Summary | Full Text:PDF(2.5MB)

A New Algorithm for the Configuration of Fast Adder Trees
Alberto PALACIOS-PAWLOVSKY 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2426-2430
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
multiplieradderWallace treepartial product additionDadda tree
 Summary | Full Text:PDF(10.7MB)

Design of C-Testable Modified-Booth Multipliers
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Vol. E83-D  No. 10 ; pp. 1868-1878
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
multipliermodified Booth Algorithmdesign for testability (DFT)C-testable design
 Summary | Full Text:PDF(873.5KB)

Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2398-2406
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagram (BDD)characteristic function (CF)multiple-output functionvariable orderinglogic simulationadderbit-counting functionmultiplier
 Summary | Full Text:PDF(563.6KB)

A Very Low Spurious Si-Bipolar Frequency Multiplier
Yo YAMAGUCHI Akihiro YAMAGISHI Akira MINAKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C  No. 7 ; pp. 1092-1097
Type of Manuscript:  Special Section PAPER (Special Issue on Microwave and Millimeter Wave Technology)
Category: Active Devices and Circuits
Keyword: 
multiplierlow spuriousSi bipolarfrequency doubler
 Summary | Full Text:PDF(787.6KB)

Minimum Cut Linear Arrangement of p-q Dags for VLSI Layout of Adder Trees
Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/05/25
Vol. E82-A  No. 5 ; pp. 767-774
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graph algorithmminimum cut linear arrangementVLSI layoutadder treemultiplier
 Summary | Full Text:PDF(690KB)

A 1-V, 1-Vp-p Input Range, Four-Quadrant Analog Multiplier Using Neuron-MOS Transistors
Koichi TANNO Okihiko ISHIZUKA Zheng TANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/05/25
Vol. E82-C  No. 5 ; pp. 750-757
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
multiplierlow voltagelow powerneuron MOS transistoranalog integrated circuit
 Summary | Full Text:PDF(435KB)

Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell
Changku HWANG Akira HYOGO Hong-sun KIM Mohammed ISMAIL Keitaro SEKINE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2 ; pp. 378-379
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog signal processingCMOSlow voltagecomposite transistormultiplier
 Summary | Full Text:PDF(143.5KB)

A High Performance Multiplier and Its Application to an FlR Filter Dedicated to Digital Video Transmission
Keisuke OKADA Shun MORIKAWA Sumitaka TAKEUCHI Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12 ; pp. 2106-2111
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
multiplierconstant coefficientFIR filtervideo transmission
 Summary | Full Text:PDF(529.8KB)

Automatic Synthesis of a Serial Input Multiprocessor Array
Dongji LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/12/25
Vol. E79-A  No. 12 ; pp. 2097-2105
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
processor arraydata-path synthesisserial interfacemultiplier
 Summary | Full Text:PDF(724.3KB)

A Design of High-Speed 4-2 Compressor for Fast Multiplier
Hiroshi MAKINO Hiroaki SUZUKI Hiroyuki MORINAKA Yasunobu NAKASE Hirofumi SHINOHARA Koichiro MASHIKO Tadashi SUMI Yasutaka HORIBA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4 ; pp. 538-548
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
4-2 compressormultiplierredundant binarytransmission gateCMOS circuit
 Summary | Full Text:PDF(1012.7KB)

A Charge-Domain D/A Conversion System
Yasuo NAGAZUMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/02/25
Vol. E79-A  No. 2 ; pp. 217-223
Type of Manuscript:  Special Section PAPER (Special Section on Analog Technologies in Submicron Era)
Category: 
Keyword: 
CCDmultiplierMDACDCTimage processing
 Summary | Full Text:PDF(580.4KB)

Partial Product Generator with Embedded Booth-Encoding
Alberto Palacios PAWLOVSKY Makoto HANAWA Kenji KANEKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12 ; pp. 1793-1795
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
partial product generatorBooth-encodingmultiplierDouble Pass-transistor Logic (DPL)modified Booth's algorithm
 Summary | Full Text:PDF(182.9KB)

4-2 Compressor with Complementary Pass-Transistor Logic
Youji KANIE Yasushi KUBOTA Shinji TOYOYAMA Yasuaki IWASE Shuhei TSUCHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Vol. E77-C  No. 4 ; pp. 647-649
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
electronic circuitsmultiplierregularly structured Wallace tree4-2 compressorcomplementary pass-transistor logic
 Summary | Full Text:PDF(174.2KB)

A Highly Drivable CMOS Design with Very Narrow Sidewall and Novel Channel Profile for 3.3 V High Speed Logic Application
Jiro IDA Satoshi ISHII Youko KAJITA Tomonobu YOKOYAMA Masayoshi INO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/04/25
Vol. E76-C  No. 4 ; pp. 525-531
Type of Manuscript:  Special Section PAPER (Special Issue on Sub-Half Micron Si Device and Process Technologies)
Category: Device Technology
Keyword: 
CMOSLDDhot-carrier-reliabilitymultiplier
 Summary | Full Text:PDF(613KB)

High Speed MOS Multiplier and Divider Using Redundant Binary Representation and Their Implementation in a Microprocessor
Shigeo KUNINOBU Tamotsu NISHIYAMA Takashi TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3 ; pp. 436-445
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
multiplierdividerredundant binarymicroprocessor
 Summary | Full Text:PDF(852.9KB)

Proposed Optoelectronic Cascadable Multiplier on GaAs LSI
Kazutoshi NAKAJIMA Yoshihiko MIZUSHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/01/25
Vol. E76-C  No. 1 ; pp. 118-123
Type of Manuscript:  Special Section PAPER (Special Issue on Opto-Electronics and LSI)
Category: Integration of Opto-Electronics and LSI Technologies
Keyword: 
optoelectronic logicmetal-semiconductor-metal photodetectorhalf-addermultiplier
 Summary | Full Text:PDF(414.3KB)

An MOS Operational Transconductance Amplifier and an MOS Four-Quadrant Analog Multiplier Using the Quadritail Cell
Katsuji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/12/25
Vol. E75-A  No. 12 ; pp. 1774-1776
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Fall Conference)
Category: 
Keyword: 
OTAmultipliertransconductancequadritail cellMOSLSI
 Summary | Full Text:PDF(155.4KB)