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Keyword : multiple-valued logic

Local Search with Probabilistic Modeling for Learning Multiple-Valued Logic Networks Shangce GAO Qiping CAO Masahiro ISHII Zheng TANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/02/01 Vol. E94-A No. 2 pp. 795-805 Type of Manuscript: PAPER Category: Neural Networks and Bioengineering Keyword: multiple-valued logic, network learning, local search, probabilistic modeling, combinatorial optimization problems,
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Multiple-Valued Data Transmission Based on Time-Domain Pre-Emphasis Techniques Yasushi YUMINAKA Yasunori TAKAHASHI Kenichi HENMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2109-2116 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Multiple-Valued VLSI Technology Keyword: pre-emphasis, high-speed interface, multiple-valued logic, equalization, data-dependent jitter,
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Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme Hirokatsu SHIRAHAMA Takashi MATSUURA Masanori NATSUI Takahiro HANYU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2080-2088 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Multiple-Valued VLSI Technology Keyword: multiple-valued logic, current-mode circuit, adaptive current control, many-core processor,
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Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits Motoi INABA Koichi TANNO Hiroki TAMURA Okihiko ISHIZUKA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2073-2079 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Multiple-Valued VLSI Technology Keyword: multiple-valued logic, overlap resolution number system, current-mode circuit, weak-inversion region,
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A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations Noboru TAKAGI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2040-2047 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: multiple-valued logic, multiple-valued logic circuits, hazard detection, delay model,
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Multiple-Valued Constant-Power Adder and Its Application to Cryptographic Processor Naofumi HOMMA Yuichi BABA Atsushi MIYAMOTO Takafumi AOKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2117-2125 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Application of Multiple-Valued VLSI Keyword: cryptographic processors, side-channel attacks, arithmetic circuits, multiple-valued logic, RSA cryptosystem,
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Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources Kwang-Jow GAN Dong-Shong LIANG Yan-Wun CHEN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 pp. 2068-2072 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Multiple-Valued VLSI Technology Keyword: multiple-valued logic, negative differential resistance, BiCMOS process,
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Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation Masatomo MIURA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 589-594 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: crosstalk, signal integrity, differential-pair circuit, multiple-valued logic,
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Design and Evaluation of a 5454-bit Multiplier Based on Differential-Pair Circuitry Akira MOCHIZUKI Hirokatsu SHIRAHAMA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 683-691 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: differential-pair circuit, current-mode circuit, multiple-valued logic,
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Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1645-1654 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: datapaths, arithmetic circuits, addition algorithms, number systems, multiple-valued logic,
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Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic Akira MOCHIZUKI Hirokatsu SHIRAHAMA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1591-1597 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: differential-pair circuit, current-mode circuit, multiple-valued logic, dynamic logic,
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Architecture of a Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic Md.Munirul HAQUE Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1869-1875 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: reconfigurable processor, multiple-valued logic, bit-serial architecture, current mode logic,
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A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI Hiroshi INOKAWA Yasuo TAKAHASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1827-1836 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: single-electron transistors, multiple-valued logic, quantum devices, logic circuits, parallel counters,
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Voltage-Mode Multiple-Valued Logic Adder Circuits Ioannis M. THOIDIS Dimitrios SOUDRIS Adonios THANAILAKIS
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/06/01 Vol. E87-C No. 6 pp. 1054-1061 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: multiple-valued logic, full adder, carry-lookahead adder, SPICE simulation,
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Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/08/01 Vol. E86-A No. 8 pp. 2001-2010 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: multiple-valued logic, signal processor, FPGAs, FIR filters,
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A Local Search Based Learning Method for Multiple-Valued Logic Networks Qi-Ping CAO Zheng TANG Rong-Long WANG Xu-Gang WANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/07/01 Vol. E86-A No. 7 pp. 1876-1884 Type of Manuscript: PAPER Category: Neural Networks and Bioengineering Keyword: multiple-valued logic, learning, MVL algebra, local search, back-propagation,
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Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits Noboru TAKAGI Kyoichi NAKASHIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/06/01 Vol. E86-A No. 6 pp. 1525-1534 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: multiple-valued logic, static hazard, prime implicants expression,
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Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/10/01 Vol. E85-C No. 10 pp. 1814-1823 Type of Manuscript: PAPER Category: Optoelectronics Keyword: interconnection problem, pass-transistor network, functional pass gate, multiple-valued logic, content-addressable memory,
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Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design Masanori NATSUI Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/09/01 Vol. E85-A No. 9 pp. 2061-2071 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and Its Applications) Category: Keyword: multiple-valued logic, arithmetic circuit, evolutionary computation, genetic algorithm (GA),
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Multiple-Valued T-Gate Based on Multiple Junction Surface Tunnel Transistor Tetsuya UEMURA Toshio BABA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/07/01 Vol. E85-C No. 7 pp. 1486-1490 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: multiple-valued logic, T-gate, flip flop, tunnel transistor, NDR,
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Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis-- Masanori NATSUI Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2808-2810 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Analog Synthesis Keyword: multiple-valued logic, arithmetic circuits, evolutionary computation, genetic algorithm,
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Heuristics to Minimize Multiple-Valued Decision Diagrams Hafiz Md. HASAN BABU Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/20 Vol. E83-A No. 12 pp. 2498-2504 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: binary decision diagram (BDD), multiple-valued decision diagram (MDD), multiple-output function, multiple-valued logic, FPGA design,
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A Logical Model for Representing Ambiguous States in Multiple-Valued Logic Systems Noboru TAKAGI Kyoichi NAKASHIMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/10/20 Vol. E82-D No. 10 pp. 1344-1351 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, set-valued functions, regularity, monotonicity, expressions,
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Design of Multiple-Valued Programmable Logic Array with Unary Function Generators Yutaka HATA Naotake KAMIURA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/09/20 Vol. E82-D No. 9 pp. 1254-1260 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, programmable logic array, unary function, logic design, minimization,
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Time-Division Multiplexing Realizations of Multiple-Output Functions Based on Shared Multi-Terminal Multiple-Valued Decision Diagrams Hafiz Md. HASAN BABU Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/05/20 Vol. E82-D No. 5 pp. 925-932 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications) Category: Logic Design Keyword: multiple-valued decision diagram (MDD), multiple-valued logic, multiple-output function, time-division multiplexing (TDM),
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10-GHz Operation of Multiple-Valued Quantizers Using Resonant-Tunneling Devices Toshihiro ITOH Takao WAHO Koichi MAEZAWA Masafumi YAMAMOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/05/20 Vol. E82-D No. 5 pp. 949-954 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications) Category: Circuits Keyword: resonant tunneling diode, HEMT, multiple-valued logic, negative differential resistance,
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A Necessary and Sufficient Condition for Kleenean Functions Noboru TAKAGI Kyoichi NAKASHIMA Masao MUKAIDONO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/11/20 Vol. E79-D No. 11 pp. 1511-1517 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: Kleenean function, fuzzy logic, Kleene algebra, multiple-valued logic, ambiguity,
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Design and Fault Masking of Two-Level Cellular Arrays on Multiple-Valued Logic Naotake KAMIURA Yutaka HATA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/10/20 Vol. E79-D No. 10 pp. 1453-1461 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: multiple-valued logic, fault masking, cellular array and switch cell,
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Impact of High-Precision Processing on the Functional Enhancement of Neuron-MOS Integrated Circuits Koji KOTANI Tadashi SHIBATA Tadahiro OHMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/03/20 Vol. E79-C No. 3 pp. 407-414 Type of Manuscript: Special Section PAPER (Special Issue on Scientific ULSI Manufacturing Technology) Category: Device Issues Keyword: high-precision processing, neuron-MOS, high-functionality circuit, ultra clean technology, multiple-valued logic,
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Minimization of Multiple-Valued Logic Expressions with Kleenean Coefficients Yutaka HATA Takahiro HOZUMI Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/03/20 Vol. E79-D No. 3 pp. 189-195 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, minimization, Kleenean functions, two-level realization, sum-of-products expression,
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On Multiple-Valued Separable Unordered Codes Yasunori NAGATA Masao MUKAIDONO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/02/20 Vol. E79-D No. 2 pp. 99-106 Type of Manuscript: PAPER Category: Algorithm and Computational Complexity Keyword: balanced codes, Berger codes, constant weight codes, multiple-valued logic, uniderectional error detection,
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Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate Xiaowei DENG Takahiro HANYU Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/08/20 Vol. E78-D No. 8 pp. 951-958 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, super pass gate, logic design, quantum devices, super pass transistor model,
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On Ternary Cellular Arrays Designed from Ternary Decision Diagrams Naotake KAMIURA Hidetoshi SATOH Yutaka HATA Kazuhara YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/04/20 Vol. E78-D No. 4 pp. 326-335 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, cellular array, ternary decision diagram and switch cell,
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A Fault Model for Multiple-Valued PLA's and Its Equivalences Yasunori NAGATA Masao MUKAIDONO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/09/20 Vol. E77-A No. 9 pp. 1527-1534 Type of Manuscript: PAPER Category: Computer Aided Design (CAD) Keyword: equivalences of faults, fault model, multiple-valued logic, programmable logic array, test compaction,
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Design of Repairable Cellular Arrays on Multiple-Valued Logic Naotake KAMIURA Yutaka HATA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1994/08/20 Vol. E77-D No. 8 pp. 877-884 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: multiple-valued logic, ecllular array, fault diagnosis, repair, design for testability,
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Low-Power 8-Valued Cellular Array VLSI for High-Speed Image Processing Takahiro HANYU Maho KUWAHARA Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/07/20 Vol. E77-C No. 7 pp. 1042-1048 Type of Manuscript: Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems) Category: Keyword: multiple-valued logic, dynamic circuits, small latency, cellular array, template matching,
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On a Class of Multiple-Valued Logic Functions with Truncated Sum, Differential Product and Not Operations Yutaka HATA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1994/05/20 Vol. E77-D No. 5 pp. 567-573 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: computer hardware and design, multiple-valued logic, truncated sum, completeness, number of the logic functions,
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A High-Density Multiple-Valued Content-Addressable Memory Based on One Transistor Cell Satoshi ARAGAKI Takahiro HANYU Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/20 Vol. E76-C No. 11 pp. 1649-1656 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: content-addressable memory, multiple-valued logic, floating-gate MOS, threshold function, logic-value conversion, relational search operation,
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Design of Wave-Parallel Computing Architectures and Its Application to Massively Parallel Image Processing Yasushi YUMINAKA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/20 Vol. E76-C No. 7 pp. 1133-1143 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Multiple-Valued Architectures and Systems Keyword: multiple-valued logic, set-valued logic, parallel processing, frequency multiplexing,
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Optical Multiplex Computing Based on Set-Valued Logic and Its Application to Parallel Sorting Networks Shuichi MAEDA Takafumi AOKI Tatsuo HIGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/20 Vol. E76-D No. 5 pp. 605-615 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Optical Logic Keyword: optical computing, optoelectronic integrated circuits, set-valued logic, multiple-valued logic, parallel processing,
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Safety Control of Power Press by Using Fail-Safe Multiple-Valued Logic Masayoshi SAKAI Masakazu KATO Koichi FUTSUHARA Masao MUKAIDONO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/20 Vol. E76-D No. 5 pp. 577-585 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Fail-Safe/Fault Tolerant Keyword: fault tolerance, multiple-valued logic, fail-safe, threshold operation, power press control,
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Some Properties and a Necessary and Sufficient Condition for Extended Kleene-Stone Logic Functions Noboru TAKAGI Kyoichi NAKASHIMA Masao MUKAIDONO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/05/20 Vol. E76-D No. 5 pp. 533-539 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Logic) Category: Logic and Logic Functions Keyword: fuzzy logic, multiple-valued logic, Kleene-Stone algebras, partial order relation,
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LSI Implementation and Safety Verification of Window Comparator Used in Fail-Safe Multiple-Valued Logic Operations Masakazu KATO Masayoshi SAKAI Koji JINKAWA Koichi FUTSUHARA Masao MUKAIDONO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/20 Vol. E76-C No. 3 pp. 419-427 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: fault tolerance, multiple-valued logic, fail-safe, threshold operation, threshold operation device,
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Neuron MOS Voltage-Mode Circuit Technology for Multiple-Valued Logic Tadashi SHIBATA Tadahiro OHMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/20 Vol. E76-C No. 3 pp. 347-356 Type of Manuscript: INVITED PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: neuron mos transistor, functional device, voltage mode computation, multiple-valued logic, universal literal,
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VLSI-Oriented Multiple-Valued Current-Mode Arithmetic Circuits Using Redundant Number Representations Shoji KAWAHITO Yasuhiro MITSUI Tetsuro NAKAMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/20 Vol. E76-C No. 3 pp. 446-454 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: multiple-valued logic, multiple-valued current-mode circuits, carry-propagation-free addition, high-speed arithmetic, VLSI,
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Multiple-Valued Static Random-Access-Memory Design and Application Zheng TANG Okihiko ISHIZUKA Hiroki MATSUMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/03/20 Vol. E76-C No. 3 pp. 403-411 Type of Manuscript: Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits) Category: Keyword: multiple-valued logic, static random-access-memory, MOS devices, integrated circuits, flip-flops, multi-stable,
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A Characterization of Kleene-Stone Logic Functions Noboru TAKAGI Masao MUKAIDONO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/02/20 Vol. E76-D No. 2 pp. 171-178 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, Kleene-Stone algebra, Kleene-Stone logic function, logic formula, partial order relation,
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Some Properties of Kleene-Stone Logic Functions and Their Canonical Disjunctive Form Noboru TAKAGI Masao MUKAIDONO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/02/20 Vol. E76-D No. 2 pp. 163-170 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: multiple-valued logic, Kleene-Stone algebra, logic formula, partial order relation, canonical disjunctive form,
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