Keyword : multiple-valued logic


Automatic Generation System for Multiple-Valued Galois-Field Parallel Multipliers
Rei UENO Naofumi HOMMA Takafumi AOKI 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8 ; pp. 1603-1610
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
Keyword: 
GF arithmetic circuitsformal designparallel multipliersautomatic generationmultiple-valued logic
 Summary | Full Text:PDF(979.3KB)

Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip
Akira MOCHIZUKI Hirokatsu SHIRAHAMA Yuma WATANABE Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/09/01
Vol. E97-D  No. 9 ; pp. 2304-2311
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Communication for VLSI
Keyword: 
asynchronous communication linknetwork-on-chipmultiple-valued logiccurrent-mode
 Summary | Full Text:PDF(1MB)

Local Search with Probabilistic Modeling for Learning Multiple-Valued Logic Networks
Shangce GAO Qiping CAO Masahiro ISHII Zheng TANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/02/01
Vol. E94-A  No. 2 ; pp. 795-805
Type of Manuscript:  PAPER
Category: Neural Networks and Bioengineering
Keyword: 
multiple-valued logicnetwork learninglocal searchprobabilistic modelingcombinatorial optimization problems
 Summary | Full Text:PDF(657.6KB)

Multiple-Valued Constant-Power Adder and Its Application to Cryptographic Processor
Naofumi HOMMA Yuichi BABA Atsushi MIYAMOTO Takafumi AOKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2117-2125
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Application of Multiple-Valued VLSI
Keyword: 
cryptographic processorsside-channel attacksarithmetic circuitsmultiple-valued logicRSA cryptosystem
 Summary | Full Text:PDF(977KB)

Multiple-Valued Data Transmission Based on Time-Domain Pre-Emphasis Techniques
Yasushi YUMINAKA Yasunori TAKAHASHI Kenichi HENMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2109-2116
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Multiple-Valued VLSI Technology
Keyword: 
pre-emphasishigh-speed interfacemultiple-valued logicequalizationdata-dependent jitter
 Summary | Full Text:PDF(1.1MB)

A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations
Noboru TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2040-2047
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
multiple-valued logicmultiple-valued logic circuitshazard detectiondelay model
 Summary | Full Text:PDF(170KB)

Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme
Hirokatsu SHIRAHAMA Takashi MATSUURA Masanori NATSUI Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2080-2088
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Multiple-Valued VLSI Technology
Keyword: 
multiple-valued logiccurrent-mode circuitadaptive current controlmany-core processor
 Summary | Full Text:PDF(1.4MB)

Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources
Kwang-Jow GAN Dong-Shong LIANG Yan-Wun CHEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2068-2072
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Multiple-Valued VLSI Technology
Keyword: 
multiple-valued logicnegative differential resistance BiCMOS process
 Summary | Full Text:PDF(291.7KB)

Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits
Motoi INABA Koichi TANNO Hiroki TAMURA Okihiko ISHIZUKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2073-2079
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Multiple-Valued VLSI Technology
Keyword: 
multiple-valued logicoverlap resolution number systemcurrent-mode circuitweak-inversion region
 Summary | Full Text:PDF(678.3KB)

Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation
Masatomo MIURA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 589-594
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
crosstalksignal integritydifferential-pair circuitmultiple-valued logic
 Summary | Full Text:PDF(736.7KB)

Design and Evaluation of a 5454-bit Multiplier Based on Differential-Pair Circuitry
Akira MOCHIZUKI Hirokatsu SHIRAHAMA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 683-691
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
differential-pair circuitcurrent-mode circuitmultiple-valued logic
 Summary | Full Text:PDF(1.5MB)

Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic
Akira MOCHIZUKI Hirokatsu SHIRAHAMA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1591-1597
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
differential-pair circuitcurrent-mode circuitmultiple-valued logicdynamic logic
 Summary | Full Text:PDF(1.2MB)

Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic
Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1645-1654
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
datapathsarithmetic circuitsaddition algorithmsnumber systemsmultiple-valued logic
 Summary | Full Text:PDF(856KB)

A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic
Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI Hiroshi INOKAWA Yasuo TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1827-1836
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
single-electron transistorsmultiple-valued logicquantum deviceslogic circuitsparallel counters
 Summary | Full Text:PDF(1.1MB)

Architecture of a Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic
Md.Munirul HAQUE Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1869-1875
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
reconfigurable processormultiple-valued logicbit-serial architecturecurrent mode logic
 Summary | Full Text:PDF(613.6KB)

Voltage-Mode Multiple-Valued Logic Adder Circuits
Ioannis M. THOIDIS Dimitrios SOUDRIS Adonios THANAILAKIS 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6 ; pp. 1054-1061
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
multiple-valued logicfull addercarry-lookahead adderSPICE simulation
 Summary | Full Text:PDF(1MB)

Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic
Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/08/01
Vol. E86-A  No. 8 ; pp. 2001-2010
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
multiple-valued logicsignal processorFPGAsFIR filters
 Summary | Full Text:PDF(2.9MB)

A Local Search Based Learning Method for Multiple-Valued Logic Networks
Qi-Ping CAO Zheng TANG Rong-Long WANG  Xu-Gang WANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/07/01
Vol. E86-A  No. 7 ; pp. 1876-1884
Type of Manuscript:  PAPER
Category: Neural Networks and Bioengineering
Keyword: 
multiple-valued logiclearningMVL algebralocal searchback-propagation
 Summary | Full Text:PDF(401.7KB)

Mathematical Foundation on Static Hazards in Multiple-Valued Logic Circuits
Noboru TAKAGI Kyoichi NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/06/01
Vol. E86-A  No. 6 ; pp. 1525-1534
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
multiple-valued logicstatic hazardprime implicants expression
 Summary | Full Text:PDF(288.5KB)

Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit
Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/10/01
Vol. E85-C  No. 10 ; pp. 1814-1823
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
interconnection problempass-transistor networkfunctional pass gatemultiple-valued logiccontent-addressable memory
 Summary | Full Text:PDF(1.5MB)

Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design
Masanori NATSUI Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/09/01
Vol. E85-A  No. 9 ; pp. 2061-2071
Type of Manuscript:  Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
Category: 
Keyword: 
multiple-valued logicarithmetic circuitevolutionary computationgenetic algorithm (GA)
 Summary | Full Text:PDF(1.2MB)

Multiple-Valued T-Gate Based on Multiple Junction Surface Tunnel Transistor
Tetsuya UEMURA Toshio BABA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/07/01
Vol. E85-C  No. 7 ; pp. 1486-1490
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
multiple-valued logicT-gateflip floptunnel transistorNDR
 Summary | Full Text:PDF(389.6KB)

Evolutionary Graph Generation System with Terminal-Color Constraint--An Application to Multiple-Valued Logic Circuit Synthesis--
Masanori NATSUI Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2808-2810
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Analog Synthesis
Keyword: 
multiple-valued logicarithmetic circuitsevolutionary computationgenetic algorithm
 Summary | Full Text:PDF(343.3KB)

Heuristics to Minimize Multiple-Valued Decision Diagrams
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2498-2504
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
binary decision diagram (BDD)multiple-valued decision diagram (MDD)multiple-output functionmultiple-valued logicFPGA design
 Summary | Full Text:PDF(451.2KB)

A Logical Model for Representing Ambiguous States in Multiple-Valued Logic Systems
Noboru TAKAGI Kyoichi NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/10/25
Vol. E82-D  No. 10 ; pp. 1344-1351
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
multiple-valued logicset-valued functionsregularitymonotonicityexpressions
 Summary | Full Text:PDF(407.1KB)

Design of Multiple-Valued Programmable Logic Array with Unary Function Generators
Yutaka HATA Naotake KAMIURA Kazuharu YAMATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/09/25
Vol. E82-D  No. 9 ; pp. 1254-1260
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
multiple-valued logicprogrammable logic arrayunary functionlogic designminimization
 Summary | Full Text:PDF(1.1MB)

Time-Division Multiplexing Realizations of Multiple-Output Functions Based on Shared Multi-Terminal Multiple-Valued Decision Diagrams
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/05/25
Vol. E82-D  No. 5 ; pp. 925-932
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications)
Category: Logic Design
Keyword: 
multiple-valued decision diagram (MDD)multiple-valued logicmultiple-output functiontime-division multiplexing (TDM)
 Summary | Full Text:PDF(411.7KB)

10-GHz Operation of Multiple-Valued Quantizers Using Resonant-Tunneling Devices
Toshihiro ITOH Takao WAHO Koichi MAEZAWA Masafumi YAMAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/05/25
Vol. E82-D  No. 5 ; pp. 949-954
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic and Its Applications)
Category: Circuits
Keyword: 
resonant tunneling diodeHEMTmultiple-valued logicnegative differential resistance
 Summary | Full Text:PDF(675.7KB)

A Necessary and Sufficient Condition for Kleenean Functions
Noboru TAKAGI Kyoichi NAKASHIMA Masao MUKAIDONO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/11/25
Vol. E79-D  No. 11 ; pp. 1511-1517
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
Kleenean functionfuzzy logicKleene algebramultiple-valued logicambiguity
 Summary | Full Text:PDF(565.5KB)

Design and Fault Masking of Two-Level Cellular Arrays on Multiple-Valued Logic
Naotake KAMIURA Yutaka HATA Kazuharu YAMATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10 ; pp. 1453-1461
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
multiple-valued logicfault maskingcellular array and switch cell
 Summary | Full Text:PDF(758.7KB)

Minimization of Multiple-Valued Logic Expressions with Kleenean Coefficients
Yutaka HATA Takahiro HOZUMI Kazuharu YAMATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/03/25
Vol. E79-D  No. 3 ; pp. 189-195
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
multiple-valued logicminimizationKleenean functionstwo-level realizationsum-of-products expression
 Summary | Full Text:PDF(578.5KB)

Impact of High-Precision Processing on the Functional Enhancement of Neuron-MOS Integrated Circuits
Koji KOTANI Tadashi SHIBATA Tadahiro OHMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/03/25
Vol. E79-C  No. 3 ; pp. 407-414
Type of Manuscript:  Special Section PAPER (Special Issue on Scientific ULSI Manufacturing Technology)
Category: Device Issues
Keyword: 
high-precision processingneuron-MOShigh-functionality circuitultra clean technologymultiple-valued logic
 Summary | Full Text:PDF(729.7KB)

On Multiple-Valued Separable Unordered Codes
Yasunori NAGATA Masao MUKAIDONO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/02/25
Vol. E79-D  No. 2 ; pp. 99-106
Type of Manuscript:  PAPER
Category: Algorithm and Computational Complexity
Keyword: 
balanced codesBerger codesconstant weight codesmultiple-valued logicuniderectional error detection
 Summary | Full Text:PDF(609KB)

Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate
Xiaowei DENG Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/08/25
Vol. E78-D  No. 8 ; pp. 951-958
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
multiple-valued logicsuper pass gatelogic designquantum devicessuper pass transistor model
 Summary | Full Text:PDF(697KB)

On Ternary Cellular Arrays Designed from Ternary Decision Diagrams
Naotake KAMIURA Hidetoshi SATOH Yutaka HATA Kazuhara YAMATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/04/25
Vol. E78-D  No. 4 ; pp. 326-335
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
multiple-valued logiccellular arrayternary decision diagram and switch cell
 Summary | Full Text:PDF(790.1KB)

A Fault Model for Multiple-Valued PLA's and Its Equivalences
Yasunori NAGATA Masao MUKAIDONO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/09/25
Vol. E77-A  No. 9 ; pp. 1527-1534
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
equivalences of faultsfault modelmultiple-valued logicprogrammable logic arraytest compaction
 Summary | Full Text:PDF(551KB)

Design of Repairable Cellular Arrays on Multiple-Valued Logic
Naotake KAMIURA Yutaka HATA Kazuharu YAMATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/08/25
Vol. E77-D  No. 8 ; pp. 877-884
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
multiple-valued logicecllular arrayfault diagnosisrepairdesign for testability
 Summary | Full Text:PDF(672.9KB)

Low-Power 8-Valued Cellular Array VLSI for High-Speed Image Processing
Takahiro HANYU Maho KUWAHARA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/07/25
Vol. E77-C  No. 7 ; pp. 1042-1048
Type of Manuscript:  Special Section PAPER (Special Issue on Super Chip for Intelligent Integrated Systems)
Category: 
Keyword: 
multiple-valued logicdynamic circuitssmall latencycellular arraytemplate matching
 Summary | Full Text:PDF(760.4KB)

On a Class of Multiple-Valued Logic Functions with Truncated Sum, Differential Product and Not Operations
Yutaka HATA Kazuharu YAMATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/05/25
Vol. E77-D  No. 5 ; pp. 567-573
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
computer hardware and designmultiple-valued logictruncated sumcompletenessnumber of the logic functions
 Summary | Full Text:PDF(466.4KB)

A High-Density Multiple-Valued Content-Addressable Memory Based on One Transistor Cell
Satoshi ARAGAKI Takahiro HANYU Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1649-1656
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: Application Specific Memory
Keyword: 
content-addressable memorymultiple-valued logicfloating-gate MOSthreshold functionlogic-value conversionrelational search operation
 Summary | Full Text:PDF(608.8KB)

Design of Wave-Parallel Computing Architectures and Its Application to Massively Parallel Image Processing
Yasushi YUMINAKA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7 ; pp. 1133-1143
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Multiple-Valued Architectures and Systems
Keyword: 
multiple-valued logicset-valued logicparallel processingfrequency multiplexing
 Summary | Full Text:PDF(1013.4KB)

Optical Multiplex Computing Based on Set-Valued Logic and Its Application to Parallel Sorting Networks
Shuichi MAEDA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/25
Vol. E76-D  No. 5 ; pp. 605-615
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic)
Category: Optical Logic
Keyword: 
optical computingoptoelectronic integrated circuitsset-valued logicmultiple-valued logicparallel processing
 Summary | Full Text:PDF(1009.1KB)

Safety Control of Power Press by Using Fail-Safe Multiple-Valued Logic
Masayoshi SAKAI Masakazu KATO Koichi FUTSUHARA Masao MUKAIDONO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/25
Vol. E76-D  No. 5 ; pp. 577-585
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic)
Category: Fail-Safe/Fault Tolerant
Keyword: 
fault tolerancemultiple-valued logicfail-safethreshold operationpower press control
 Summary | Full Text:PDF(752.5KB)

Some Properties and a Necessary and Sufficient Condition for Extended Kleene-Stone Logic Functions
Noboru TAKAGI Kyoichi NAKASHIMA Masao MUKAIDONO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/05/25
Vol. E76-D  No. 5 ; pp. 533-539
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Logic)
Category: Logic and Logic Functions
Keyword: 
fuzzy logicmultiple-valued logicKleene-Stone algebraspartial order relation
 Summary | Full Text:PDF(569.2KB)

Multiple-Valued Static Random-Access-Memory Design and Application
Zheng TANG Okihiko ISHIZUKA Hiroki MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3 ; pp. 403-411
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
multiple-valued logicstatic random-access-memoryMOS devicesintegrated circuitsflip-flopsmulti-stable
 Summary | Full Text:PDF(617.3KB)

LSI Implementation and Safety Verification of Window Comparator Used in Fail-Safe Multiple-Valued Logic Operations
Masakazu KATO Masayoshi SAKAI Koji JINKAWA Koichi FUTSUHARA Masao MUKAIDONO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3 ; pp. 419-427
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
fault tolerancemultiple-valued logicfail-safethreshold operationthreshold operation device
 Summary | Full Text:PDF(808.4KB)

Neuron MOS Voltage-Mode Circuit Technology for Multiple-Valued Logic
Tadashi SHIBATA Tadahiro OHMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3 ; pp. 347-356
Type of Manuscript:  INVITED PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
neuron mos transistorfunctional devicevoltage mode computationmultiple-valued logicuniversal literal
 Summary | Full Text:PDF(962.7KB)

VLSI-Oriented Multiple-Valued Current-Mode Arithmetic Circuits Using Redundant Number Representations
Shoji KAWAHITO Yasuhiro MITSUI Tetsuro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3 ; pp. 446-454
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
multiple-valued logicmultiple-valued current-mode circuitscarry-propagation-free additionhigh-speed arithmeticVLSI
 Summary | Full Text:PDF(728.2KB)

A Characterization of Kleene-Stone Logic Functions
Noboru TAKAGI Masao MUKAIDONO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/02/25
Vol. E76-D  No. 2 ; pp. 171-178
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
multiple-valued logicKleene-Stone algebraKleene-Stone logic functionlogic formulapartial order relation
 Summary | Full Text:PDF(624.2KB)

Some Properties of Kleene-Stone Logic Functions and Their Canonical Disjunctive Form
Noboru TAKAGI Masao MUKAIDONO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/02/25
Vol. E76-D  No. 2 ; pp. 163-170
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
multiple-valued logicKleene-Stone algebralogic formulapartial order relationcanonical disjunctive form
 Summary | Full Text:PDF(619.9KB)