A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations Noboru TAKAGI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-DNo. 8 ;
pp. 2040-2047 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: Logic Design Keyword: multiple-valued logic, multiple-valued logic circuits, hazard detection, delay model,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/07/25 Vol. E76-ANo. 7 ;
pp. 1087-1096 Type of Manuscript: Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I) Category: Keyword: M-D digital filter, multiple-valued logic circuits, signal processor,
