Keyword : multicycle communication

A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication
Chia-I CHEN  Juinn-Dar HUANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7  pp. 1300-1308
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword: 
multicycle communication,  architectural synthesis,  high-level synthesis,  performance-driven,  criticality-driven, 
  Summary |  Full Text:PDF
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
Ya-Shih HUANG  Yu-Ju HONG  Juinn-Dar HUANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12  pp. 3143-3150
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
multicycle communication,  communication synthesis,  interconnect minimization,  resource allocation,  resource sharing,  scheduling,  routing, 
  Summary |  Full Text:PDF