Keyword : message-passing algorithm


Ring Theoretic Approach to Reversible Codes Based on Circulant Matrices
Tomoharu SHIBUYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11 ; pp. 2121-2126
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
LDPC codesreversible codesencoding of linear codesJacobi methodcirculant matricesmessage-passing algorithm
 Summary | Full Text:PDF(158.4KB)

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
Kazunori SHIMIZU Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4 ; pp. 1054-1061
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low-density parity-check codemessage-passing algorithmintermediate message compression techniqueclock gated shift register for intermediate message
 Summary | Full Text:PDF(451.3KB)

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule
Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3602-3612
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low-density parity-check codesparallel LDPC decoder architecturemessage-passing algorithmFIFO-based buffering
 Summary | Full Text:PDF(1017.1KB)

Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule
Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 969-978
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low-density parity-check codespartially-parallel LDPC decodermessage-passing algorithmFPGA
 Summary | Full Text:PDF(748.2KB)