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Keyword : low-power
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Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches
Kyundong KIM
Seidai TAKEDA
Shinobu MIWA
Hiroshi NAKAMURA
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12
pp. 2301-2308
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword:
low-power,
cache,
leakage power,
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A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop
Hsin-Shu CHEN
Jyun-Cheng LIN
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C
No. 6
pp. 855-860
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category:
Keyword:
delay-locked loop,
fast-lock,
low-power,
subranging,
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Phase Compensation Techniques for Low-Power Operational Amplifiers
Rui ITO
Tetsuro ITAKURA
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C
No. 6
pp. 730-740
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: INVITED
Keyword:
low-power,
operational amplifier (opamp),
phase-compensation,
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A New Energy Delay-Aware Flip-Flop
Inhwa JUNG
Moo-young KIM
Dongsuk SHIN
Seon Wook KIM
Chulwoo KIM
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A
No. 6
pp. 1552-1557
Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category:
Keyword:
flip-flop,
pulsed-latch,
low-power,
high-speed,
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Power-Aware Scalable Pipelined Booth Multiplier
Hanho LEE
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/11/01
Vol. E88-A
No. 11
pp. 3230-3234
Type of Manuscript: LETTER
Category: VLSI Design Technology and CAD
Keyword:
power-aware,
pipelined,
Booth multiplier,
low-power,
design,
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A Low-Power Architecture for Extended Finite State Machines Using Input Gating
Shi-Yu HUANG
Chien-Jyh LIU
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A
No. 12
pp. 3109-3115
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword:
low-power,
architecture,
VLSI design,
FSM,
gating,
synthesis,
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µI/O Architecture: A Power-Aware Interconnect Circuit Design for SoC and SiP
Yusuke KANNO
Hiroyuki MIZUNO
Nobuhiro OODAIRA
Yoshihiko YASU
Kazumasa YANAGISAWA
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C
No. 4
pp. 589-597
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category:
Keyword:
low-cost,
System-on-Chip,
SoC,
System-in-Package,
SiP,
hierarchical I/O design,
signal-level converter,
signal wall function,
low-power,
interconnect circuit,
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A 1.5 V, 200 MHz, 400 MIPS, 188 µA/MHz and 1.2 V, 300 MHz, 600 MIPS, 169 µA/MHz Digital Signal Processor Core for 3G Wireless Applications
Hiroshi TAKAHASHI
Shigeshi ABIKO
Kenichi TASHIRO
Kaoru AWAKA
Yutaka TOYONOH
Rimon IKENO
Shigetoshi MURAMATSU
Yasumasa IKEZAKI
Tsuyoshi TANAKA
Akihiro TAKEGAMA
Hiroshi KIMIZUKA
Hidehiko NITTA
Miki KOJIMA
Masaharu SUZUKI
James Lowell LARIMER
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Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C
No. 4
pp. 491-501
Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category:
Keyword:
200 MHz,
300 MHz,
400 MIPS,
600 MIPS,
high-speed,
low-power,
fixed point DSP,
130 nm,
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Fast and Low Power Viterbi Search Engine Using Inverse Hidden Markov Model
Bo-Sung KIM
Jun-Dong CHO
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A
No. 3
pp. 695-697
Type of Manuscript: Special Section LETTER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Communication Theory and Systems
Keyword:
VLSI,
HMM,
Viterbi search,
low-power,
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Reducing Cache Energy Dissipation by Using Dual Voltage Supply
Vasily G. MOSHNYAGA
Hiroshi TSUJI
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Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A
No. 11
pp. 2762-2768
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword:
cache,
processor architecture,
low-power,
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